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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-15 14:18:31 (GMT)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-15 14:18:31 (GMT)
commit6579d15c58e2b6b051f126ea8b77dd767252aa14 (patch)
treecac9f9205db8c28a764ad8282d3a909bf95e8db4 /arch/arm/cpu/armv7
parentc44bb3a30f5a1332176edce1a91c0e2cf666ee8f (diff)
parent19a0f7fa271de0345bb2df90d443c547c41e8037 (diff)
downloadu-boot-fsl-qoriq-6579d15c58e2b6b051f126ea8b77dd767252aa14.tar.xz
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/Makefile2
-rw-r--r--arch/arm/cpu/armv7/config.mk2
-rw-r--r--arch/arm/cpu/armv7/mx6/Makefile1
-rw-r--r--arch/arm/cpu/armv7/mx6/lowlevel_init.S35
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c16
5 files changed, 18 insertions, 38 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ee8c2b3..4668b3c 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS += cache_v7.o
COBJS += cpu.o
COBJS += syslib.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index 350e946..9c3e2f3 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -40,5 +40,5 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),)
-ALL-y += $(OBJTREE)/u-boot.imx
+ALL-y += $(obj)u-boot.imx
endif
diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile
index cbce411..4f9ca68 100644
--- a/arch/arm/cpu/armv7/mx6/Makefile
+++ b/arch/arm/cpu/armv7/mx6/Makefile
@@ -28,7 +28,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = soc.o clock.o
-SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S b/arch/arm/cpu/armv7/mx6/lowlevel_init.S
deleted file mode 100644
index 7b60ca7..0000000
--- a/arch/arm/cpu/armv7/mx6/lowlevel_init.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-.section ".text.init", "x"
-
-#include <linux/linkage.h>
-
-.macro init_arm_errata
- /* ARM erratum ID #743622 */
- mrc p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orr r10, r10, #1 << 6 /* set bit #6 */
- /* ARM erratum ID #751472 */
- orr r10, r10, #1 << 11 /* set bit #11 */
- mcr p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-.endm
-
-ENTRY(lowlevel_init)
- init_arm_errata
- mov pc, lr
-ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a8aad5d..193ba12 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -30,6 +30,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+#include <stdbool.h>
struct scu_regs {
u32 ctrl;
@@ -121,12 +122,23 @@ void set_vddsoc(u32 mv)
writel(reg, &anatop->reg_core);
}
+static void imx_set_wdog_powerdown(bool enable)
+{
+ struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+
+ /* Write to the PDE (Power Down Enable) bit */
+ writew(enable, &wdog1->wmcr);
+ writew(enable, &wdog2->wmcr);
+}
+
int arch_cpu_init(void)
{
init_aips();
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
+ imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
return 0;
}
@@ -193,3 +205,7 @@ const struct boot_mode soc_boot_modes[] = {
{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
+
+void s_init(void)
+{
+}