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| author | Tom Rini <trini@konsulko.com> | 2017-01-19 17:22:23 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-19 17:22:23 (GMT) |
| commit | 0675f992dbf4a785a05a1baf149c2bce6aa5fe90 (patch) | |
| tree | b8868ec70ff6b2b20f8f0fb87df9438906020a08 /arch/arm/cpu/armv8/start.S | |
| parent | 755b06d1c0f3b16318c7580bec066efbb9ec6ccf (diff) | |
| parent | 5e4a6db8f428cb1f8ced74bc77241144ac0c5b1a (diff) | |
| download | u-boot-fsl-qoriq-0675f992dbf4a785a05a1baf149c2bce6aa5fe90.tar.xz | |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv8/start.S')
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 9535057..62d97f7 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -85,6 +85,17 @@ save_boot_params_ret: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: + /* + * Enalbe SMPEN bit for coherency. + * This register is not architectural but at the moment + * this bit should be set for A53/A57/A72. + */ +#ifdef CONFIG_ARMV8_SET_SMPEN + mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ + orr x0, x0, #0x40 + msr S3_1_c15_c2_1, x0 +#endif + /* Apply ARM core specific erratas */ bl apply_core_errata @@ -250,14 +261,14 @@ WEAK(lowlevel_init) /* * All slaves will enter EL2 and optionally EL1. */ - adr x3, lowlevel_in_el2 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el2 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el2 lowlevel_in_el2: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x3, lowlevel_in_el1 - ldr x4, =ES_TO_AARCH64 + adr x4, lowlevel_in_el1 + ldr x5, =ES_TO_AARCH64 bl armv8_switch_to_el1 lowlevel_in_el1: |