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authorMarek Vasut <marex@denx.de>2014-09-08 12:08:45 (GMT)
committerMarek Vasut <marex@denx.de>2014-10-06 15:46:49 (GMT)
commite9d6a20034788258bc5008dc2665aabe9ce28b1c (patch)
tree5f02fb8a2a83c4983a92daed5e0e3b1c4678b1e1 /arch/arm/cpu
parent2110eeaf0fdf9b3b200076554d266459ca7ac26d (diff)
downloadu-boot-fsl-qoriq-e9d6a20034788258bc5008dc2665aabe9ce28b1c.tar.xz
arm: socfpga: reset: Add EMAC reset functions
Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/socfpga/reset_manager.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 5d7aba4..badc569 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -49,3 +49,20 @@ void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per_mod_reset);
}
+
+/* Change the reset state for EMAC 0 and EMAC 1 */
+void socfpga_emac_reset(int enable)
+{
+ const void *reset = &reset_manager_base->per_mod_reset;
+
+ if (enable) {
+ setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+ setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+ } else {
+#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+#endif
+ }
+}