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authorPeng Fan <peng.fan@nxp.com>2016-12-11 11:24:30 (GMT)
committerStefano Babic <sbabic@denx.de>2016-12-16 10:38:24 (GMT)
commita472e9bd6a51d67de38ca8fe65e1df344d19849e (patch)
treedb5511b04e377ebe4e3a419940ef3155d28bcc69 /arch/arm/imx-common/cache.c
parentdfca246f4cbc46b5bb714b611dcbd3f5eae3b1e6 (diff)
downloadu-boot-fsl-qoriq-a472e9bd6a51d67de38ca8fe65e1df344d19849e.tar.xz
imx-common: cache: configure L2 Cache for i.MX6SLL
If L2 cache configured as OCRAM, reset it. Switch to use runtime check. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/imx-common/cache.c')
-rw-r--r--arch/arm/imx-common/cache.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index b775488..1c4a9a2 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -8,6 +8,7 @@
#include <asm/armv7.h>
#include <asm/pl310.h>
#include <asm/io.h>
+#include <asm/imx-common/sys_proto.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
@@ -39,6 +40,7 @@ void enable_caches(void)
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned int val;
@@ -55,15 +57,14 @@ void v7_outer_cache_enable(void)
*/
setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
-#if defined CONFIG_MX6SL
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
- /* L2 cache configured as OCRAM, reset it */
- val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
- writel(val, &iomux->gpr[11]);
+ if (is_mx6sl() || is_mx6sll()) {
+ val = readl(&iomux->gpr[11]);
+ if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+ /* L2 cache configured as OCRAM, reset it */
+ val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+ writel(val, &iomux->gpr[11]);
+ }
}
-#endif
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);