Merge branch 'master' into scalys

10 files changed, 42 insertions, 50 deletions

diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 30e66ba..d34a784 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -68,7 +68,7 @@ SPL: spl/u-boot-spl.bin $(IMX_CONFIG) FORCE
 	$(call if_changed,mkimage)
 
 MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
-		-e $(CONFIG_SYS_TEXT_BASE) -C none
+		-e $(CONFIG_SYS_TEXT_BASE) -C none -T firmware
 
 u-boot.uim: u-boot.bin FORCE
 	$(call if_changed,mkimage)
@@ -86,7 +86,7 @@ u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
 	$(call if_changed,pad_cat)
 
 quiet_cmd_u-boot-nand-spl_imx = GEN     $@
-cmd_u-boot-nand-spl_imx = (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
+cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \
 	dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@
 
 spl/u-boot-nand-spl.imx: SPL FORCE
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index 54b021c..b775488 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -43,6 +43,12 @@ void v7_outer_cache_enable(void)
 
 
 	/*
+	 * Must disable the L2 before changing the latency parameters
+	 * and auxiliary control register.
+	 */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+	/*
 	 * Set bit 22 in the auxiliary control register. If this bit
 	 * is cleared, PL310 treats Normal Shared Non-cacheable
 	 * accesses as Cacheable no-allocate.
@@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
 	}
 #endif
 
-	/* Must disable the L2 before changing the latency parameters */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);
 
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 656bb60..4223187 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -137,6 +137,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_MX7S:
+		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
 		return "7D";	/* Dual-core version of the mx7 */
 	case MXC_CPU_MX6QP:
diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c
index daf3c7e..9bc56f6 100644
--- a/arch/arm/imx-common/ddrmc-vf610.c
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -212,7 +212,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 			cr_setting++;
 		}
 
-	/* perform default PHY settings (may be overriden by custom settings */
+	/* perform default PHY settings (may be overridden by custom settings */
 	phy_setting = default_phy_settings;
 	while (phy_setting->phy_rnum >= 0) {
 		writel(phy_setting->setting,
diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index 8bbcc22..6731825 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -17,60 +17,55 @@
 
 #define hab_rvt_report_event_p					\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dqp()) ?						\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
+	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)	\
 )
 
 #define hab_rvt_report_status_p					\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)	\
 )
 
 #define hab_rvt_authenticate_image_p				\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)	\
 )
 
 #define hab_rvt_entry_p						\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dqp()) ?						\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
+	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY)			\
 )
 
 #define hab_rvt_exit_p						\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT)			\
 )
@@ -424,8 +419,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 			 */
 			/* Check MMU enabled */
 			if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
-				if (is_cpu_type(MXC_CPU_MX6Q) ||
-				    is_cpu_type(MXC_CPU_MX6D)) {
+				if (is_mx6dq()) {
 					/*
 					 * This won't work on Rev 1.0.0 of
 					 * i.MX6Q/D, since their ROM doesn't
@@ -434,10 +428,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 					 */
 					if (!is_mx6dqp())
 						writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
-				} else if (is_cpu_type(MXC_CPU_MX6DL) ||
-					   is_cpu_type(MXC_CPU_MX6SOLO)) {
+				} else if (is_mx6sdl()) {
 					writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
-				} else if (is_cpu_type(MXC_CPU_MX6SL)) {
+				} else if (is_mx6sl()) {
 					writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
 				}
 			}
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
index 15dab1d..3d2ce3a 100644
--- a/arch/arm/imx-common/init.c
+++ b/arch/arm/imx-common/init.c
@@ -44,7 +44,7 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr3);
 	writel(0x00000000, &aips2->opacr4);
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+	if (is_mx6sx() || is_mx7()) {
 		/*
 		 * Set all MPROTx to be non-bufferable, trusted for R/W,
 		 * not forced to user-mode.
@@ -78,8 +78,7 @@ void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog1->wmcr);
 	writew(enable, &wdog2->wmcr);
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
-			is_soc_type(MXC_SOC_MX7))
+	if (is_mx6sx() || is_mx6ul() || is_mx7())
 		writew(enable, &wdog3->wmcr);
 #ifdef CONFIG_MX7D
 	writew(enable, &wdog4->wmcr);
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 228d5f8..66137d1 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -83,7 +83,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 
 #if defined(CONFIG_MX6QDL)
 	stride = 2;
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_mx6dq())
 		p += 1;
 #else
 	stride = 1;
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index d174a46..acf9831 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -15,7 +15,7 @@ int setup_sata(void)
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_mx6dq() && !is_mx6dqp())
 		return 1;
 
 	ret = enable_sata_clock();
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index caa45cf..bdcda7d 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -70,7 +70,7 @@ u32 spl_boot_device(void)
 
 #if defined(CONFIG_SPL_MMC_SUPPORT)
 /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
 {
 	switch (spl_boot_device()) {
 	/* for MMC return either RAW or FAT mode */
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 92c7218..a01590c 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -43,10 +43,8 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
-	if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
-	    (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
-	     is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
-	     is_cpu_type(MXC_CPU_MX6UL))
+	if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
+	    is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
 		return 1;
 
 	return 0;
@@ -86,10 +84,7 @@ int timer_init(void)
 		i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
 
 		/* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
-		if (is_cpu_type(MXC_CPU_MX6DL) ||
-		    is_cpu_type(MXC_CPU_MX6SOLO) ||
-		    is_cpu_type(MXC_CPU_MX6SX) ||
-		    is_cpu_type(MXC_CPU_MX6UL)) {
+		if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
 			i |= GPTCR_24MEN;
 
 			/* Produce 3Mhz clock */