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authorChris Kuethe <chris.kuethe@gmail.com>2015-06-02 23:31:43 (GMT)
committerStefano Babic <sbabic@denx.de>2015-06-09 10:00:42 (GMT)
commit1005ccda97243bcdbf31216685885cfd4ea32f29 (patch)
tree8316915b0804944e0115582ba7dd3285a3c9ec2c /arch/arm/include/asm/arch-mx5
parent3d0158ae18bef2ac89979f4c90419d3add436c71 (diff)
downloadu-boot-fsl-qoriq-1005ccda97243bcdbf31216685885cfd4ea32f29.tar.xz
patch - arm - define SYS_CACHELINE_SIZE for mx5
mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx5')
-rw-r--r--arch/arm/include/asm/arch-mx5/imx-regs.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index f059d0f..5f0e1e6 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -9,6 +9,8 @@
#define ARCH_MXC
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_SOC_BASE_ADDR 0x40000000