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authorRoy Spliet <r.spliet@ultimaker.com>2015-05-26 15:00:41 (GMT)
committerHans de Goede <hdegoede@redhat.com>2015-05-29 11:46:36 (GMT)
commitd0f4200392515194bf67213165be906e5b9e5748 (patch)
treee9545288dd85621ce1a7bbe76d00cb706e0d395f /arch/arm/include/asm/arch-sunxi/clock_sun4i.h
parenta19e735d3cbf8fb50a69e911d107635be858c84f (diff)
downloadu-boot-fsl-qoriq-d0f4200392515194bf67213165be906e5b9e5748.tar.xz
sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMA
Make sure definitions for NAND clock and DMA gate bits are the same across boards. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/clock_sun4i.h')
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 63c3319..58aff16 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -39,7 +39,7 @@ struct sunxi_ccm_reg {
u32 apb0_gate; /* 0x68 apb0 module clock gating */
u32 apb1_gate; /* 0x6c apb1 module clock gating */
u8 res4[0x10];
- u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
+ u32 nand0_clk_cfg; /* 0x80 nand sub clock control */
u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
@@ -177,7 +177,7 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_ACE 16
#define AHB_GATE_OFFSET_DLL 15
#define AHB_GATE_OFFSET_SDRAM 14
-#define AHB_GATE_OFFSET_NAND 13
+#define AHB_GATE_OFFSET_NAND0 13
#define AHB_GATE_OFFSET_MS 12
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10