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| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2016-10-28 10:21:28 (GMT) |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2016-10-30 10:38:04 (GMT) |
| commit | 297bb9e0fc7049c7771feed5e11cf6db89b19f27 (patch) | |
| tree | 8a1ab699cd722d580e836f76c8a6bfed2a91843f /arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | |
| parent | fed329aebe3aaac0928c73547ac6316af2adf0cd (diff) | |
| download | u-boot-fsl-qoriq-297bb9e0fc7049c7771feed5e11cf6db89b19f27.tar.xz | |
sunxi: DRAM initialisation for sun9i
This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.
With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.
[wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks]
[hdegoede@redhat.com: Fix checkpatch warnings]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/cpu_sun9i.h')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index 04889c5..acbc94f 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -38,6 +38,12 @@ #define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) #define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) +#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) +#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) +#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000) +#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) +#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) + /* AHB1 Module */ #define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) #define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) |