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| author | Hans de Goede <hdegoede@redhat.com> | 2015-01-13 12:21:46 (GMT) |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-22 11:34:55 (GMT) |
| commit | 6515032e3b88f0774f93fb05deaf20e48a515fe4 (patch) | |
| tree | 7f4d251b1b4b07d64e5bff19d2e44c975498ef88 /arch/arm/include/asm/arch-sunxi/display.h | |
| parent | b56f6e2b4e0291efbe1b50f082dec73272ad7ab3 (diff) | |
| download | u-boot-fsl-qoriq-6515032e3b88f0774f93fb05deaf20e48a515fe4.tar.xz | |
sunxi: display: Make lcd display clk phase configurable
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/display.h')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/display.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 2ac8a87..ff92a10 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -249,9 +249,7 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0 (0 << 28) -#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60 (1 << 28) -#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE120 (2 << 28) +#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) #define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) |