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| author | Hans de Goede <hdegoede@redhat.com> | 2016-08-19 13:25:41 (GMT) |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2016-08-26 14:58:37 (GMT) |
| commit | 421c98d7d2ebf929debf907e75ec04419cf07dbe (patch) | |
| tree | 066fff4164e808f9f502aaed7b7793eef541b753 /arch/arm/include/asm/arch-sunxi/pwm.h | |
| parent | 8d463c5a32f7d404ee1a0cd68d4746e2ebab9e22 (diff) | |
| download | u-boot-fsl-qoriq-421c98d7d2ebf929debf907e75ec04419cf07dbe.tar.xz | |
sunxi: display: Use PWM to drive backlight where applicable
When the backlight's pwm input is connected to a pwm output of the SoC,
actually use pwm to drive the backlight.
The mean reason for doing this is to fix the backlight turning off
for aprox. 1 second while the kernel is booting. This is caused by
the kernel actually using pwm to drive the backlight, so that it
can dim the backlight. First the pwm driver loads and switches the
pinmux for the pin driving the backlight's pwm input to the pwm
controller. Then about 1s later the actual backlight driver loads
and tells the pwm driver to actually update the pwm settings, which
have a power-on-reset value of "off".
An additional advantage is that this allows us to initatiate the
backlight at 80%, which is the kernel default, avoiding a brightness
change while the kernel loads.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed by: Peter Korsgaard <peter@korsgaard.com>
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/pwm.h')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/pwm.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h new file mode 100644 index 0000000..5884b5d --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/pwm.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_PWM_H +#define _SUNXI_PWM_H + +#define SUNXI_PWM_CTRL_REG (SUNXI_PWM_BASE + 0) +#define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4) + +#define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf) +#define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4) +#define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5) + +#define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 + +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I +#define SUNXI_PWM_PIN0 SUNXI_GPB(2) +#define SUNXI_PWM_MUX SUN4I_GPB_PWM +#endif + +#if defined CONFIG_MACH_SUN6I +#define SUNXI_PWM_PIN0 SUNXI_GPH(13) +#define SUNXI_PWM_MUX SUN6I_GPH_PWM +#endif + +#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33 +#define SUNXI_PWM_PIN0 SUNXI_GPH(0) +#define SUNXI_PWM_MUX SUN8I_GPH_PWM +#endif + +#endif |