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| author | Tom Warren <twarren@nvidia.com> | 2015-06-25 16:50:44 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-08-05 22:22:51 (GMT) |
| commit | 722e000ccd7226c5cd071590b5361620eb0b126c (patch) | |
| tree | 257ddcaf4039dd6722e743e8a1f4035c2f85387f /arch/arm/include/asm/arch-tegra210 | |
| parent | 3e8650c0f9cc7fb29bd75c11d0173768fcc80203 (diff) | |
| download | u-boot-fsl-qoriq-722e000ccd7226c5cd071590b5361620eb0b126c.tar.xz | |
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra210')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h index b62e070..175040d 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -25,6 +25,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DP, /* These are the base clocks (inputs to the Tegra SoC) */ CLOCK_ID_32KHZ, |