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| author | Stephen Warren <swarren@nvidia.com> | 2015-02-24 21:08:24 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-03-04 17:08:59 (GMT) |
| commit | 7a28441f4d89cac6885a7e817e41379c83cb35aa (patch) | |
| tree | d747f8ec40905f88900e6463ec6f0422e100b137 /arch/arm/include/asm/arch-tegra30 | |
| parent | 9f21c1a378f89c6f4ee06e5aeea37c426fdec15f (diff) | |
| download | u-boot-fsl-qoriq-7a28441f4d89cac6885a7e817e41379c83cb35aa.tar.xz | |
ARM: tegra: pinmux: simplify some defines
Future SoCs have a slightly different combination of pinmux options per
pin. This will be simpler to handle if we simply have one define per
option, rather than grouping various options together, in combinations
that don't align with future chips.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra30')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra30/pinmux.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index a42e009..e9046ff 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -391,8 +391,11 @@ enum pmux_func { PMUX_FUNC_COUNT, }; -#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC -#define TEGRA_PMX_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_PINS_HAVE_E_INPUT +#define TEGRA_PMX_PINS_HAVE_LOCK +#define TEGRA_PMX_PINS_HAVE_OD +#define TEGRA_PMX_PINS_HAVE_IO_RESET #include <asm/arch-tegra/pinmux.h> #endif /* _TEGRA30_PINMUX_H_ */ |