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| author | SRICHARAN R <r.sricharan@ti.com> | 2013-11-08 12:10:37 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-04 13:12:08 (GMT) |
| commit | 6c70935d7525a4b2b144b49457d2bae85f1d111a (patch) | |
| tree | 663b91f30c048968bcef5a4bf3916b123c51f7ab /arch/arm/include/asm/emif.h | |
| parent | 39302dcd3013134e936cc76ccee8d1ed5522bfa0 (diff) | |
| download | u-boot-fsl-qoriq-6c70935d7525a4b2b144b49457d2bae85f1d111a.tar.xz | |
ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/include/asm/emif.h')
| -rw-r--r-- | arch/arm/include/asm/emif.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 1b94a99..c12beea 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -581,7 +581,6 @@ (0xFF << EMIF_SYS_ADDR_SHIFT)) #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 -#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14 /* Reg mapping structure */ struct emif_reg_struct { @@ -690,6 +689,9 @@ struct emif_reg_struct { u32 emif_ddr_ext_phy_ctrl_23_shdw; u32 emif_ddr_ext_phy_ctrl_24; u32 emif_ddr_ext_phy_ctrl_24_shdw; + u32 padding[22]; + u32 emif_ddr_fifo_misaligned_clear_1; + u32 emif_ddr_fifo_misaligned_clear_2; }; struct dmm_lisa_map_regs { |