diff options
| author | Samuel Mescoff <samuel.mescoff@mobile-devices.fr> | 2016-02-16 08:45:06 (GMT) |
|---|---|---|
| committer | Andreas Bießmann <andreas.devel@googlemail.com> | 2016-02-18 20:34:41 (GMT) |
| commit | f7cf291aa788eb5b64c0d16de529b1a378f509bb (patch) | |
| tree | 7fb741b4c492033d0b5fb364dc372dbb995898b9 /arch/arm/mach-at91/atmel_sfr.c | |
| parent | c21c28b6f39468dcc13f82458fa3c6f6c5dce9d9 (diff) | |
| download | u-boot-fsl-qoriq-f7cf291aa788eb5b64c0d16de529b1a378f509bb.tar.xz | |
ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/mach-at91/atmel_sfr.c')
| -rw-r--r-- | arch/arm/mach-at91/atmel_sfr.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 2bccb84..adf44c6 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -19,3 +19,10 @@ void redirect_int_from_saic_to_aic(void) writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir); } } + +void configure_2nd_sram_as_l2_cache(void) +{ + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + + writel(1, &sfr->l2cc_hramc); +} |