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author | Tom Rini <trini@konsulko.com> | 2017-05-18 21:17:42 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2017-05-18 21:17:42 (GMT) |
commit | 753a4dde970c2bc9022321f1093e544e3a150f6e (patch) | |
tree | 6973921effd3b964773b8f60531580ad16f18190 /arch/arm/mach-socfpga/spl.c | |
parent | a0bdf7b31d91eec702ef9b1f295bb2e8439e8f29 (diff) | |
parent | d89e979c42892db572c4ef5d56bc207075953f58 (diff) | |
download | u-boot-fsl-qoriq-753a4dde970c2bc9022321f1093e544e3a150f6e.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'arch/arm/mach-socfpga/spl.c')
-rw-r--r-- | arch/arm/mach-socfpga/spl.c | 56 |
1 files changed, 53 insertions, 3 deletions
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index fec4c7a..71bae82 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -19,23 +19,32 @@ #include <asm/arch/sdram.h> #include <asm/arch/scu.h> #include <asm/arch/nic301.h> +#include <asm/sections.h> +#include <fdtdec.h> +#include <watchdog.h> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/pinmux.h> +#endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = +#endif + +static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; u32 spl_boot_device(void) { const u32 bsel = readl(&sysmgr_regs->bootinfo); - switch (bsel & 0x7) { + switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void socfpga_nic301_slave_ns(void) { writel(0x1, &nic301_regs->lwhps2fpgaregs); @@ -127,7 +137,8 @@ void board_init_f(ulong dummy) debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ - cm_basic_init(cm_default_cfg); + if (cm_basic_init(cm_default_cfg)) + hang(); /* Enable bootrom to configure IOs. */ sysmgr_config_warmrstcfgio(1); @@ -182,3 +193,42 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +void spl_board_init(void) +{ + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* Release UART from reset */ + socfpga_reset_uart(0); + + /* enable console uart printing */ + preloader_console_init(); +} + +void board_init_f(ulong dummy) +{ + /* + * Configure Clock Manager to use intosc clock instead external osc to + * ensure success watchdog operation. We do it as early as possible. + */ + cm_use_intosc(); + + socfpga_watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + socfpga_reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ +} +#endif |