diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2016-11-30 08:54:34 (GMT) |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-04-20 11:30:01 (GMT) |
| commit | 328ce7fd505288949d83b72562586a139e025549 (patch) | |
| tree | d3d2c0f2060c1a04e1ad9020c0bcd8be49c29958 /arch/arm/mach-sunxi | |
| parent | 8094a4a20b05827d6fa91786705b3f6917f7421c (diff) | |
| download | u-boot-fsl-qoriq-328ce7fd505288949d83b72562586a139e025549.tar.xz | |
sunxi: Set PLL lock enable bits for R40
According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.
This patch enables it for all the PLLs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/mach-sunxi')
| -rw-r--r-- | arch/arm/mach-sunxi/clock_sun6i.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 4762fbf..3c8c53f 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -35,6 +35,11 @@ void clock_init_safe(void) clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); #endif +#ifdef CONFIG_MACH_SUN8I_R40 + /* Set PLL lock enable bits and switch to old lock mode */ + writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); +#endif + clock_set_pll1(408000000); writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); |