diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-01-15 05:59:03 (GMT) |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-01-17 00:00:40 (GMT) |
| commit | 78c627cf1f808d5ae9240809a81b71903bdf4fe2 (patch) | |
| tree | 9193f6e6389c787efbea9b60ef9a567a09600a2e /arch/arm/mach-uniphier/clk/clk-dram-pro5.c | |
| parent | a314a245d14547df0a88e1ea568116fd7947daf4 (diff) | |
| download | u-boot-fsl-qoriq-78c627cf1f808d5ae9240809a81b71903bdf4fe2.tar.xz | |
ARM: uniphier: split out UMC clock enable
The clock enable bits for UMC are more SoC-specific than for
the other hardware blocks. Separate the UMC clocks and the other
clocks for better code reuse across SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/clk/clk-dram-pro5.c')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/clk-dram-pro5.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c new file mode 100644 index 0000000..1edc85a --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2015-2017 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sc-regs.h" + +void uniphier_pro5_dram_clk_init(void) +{ + u32 tmp; + + /* + * deassert reset + * UMCA2: Ch1 (DDR3) + * UMCA1, UMC31: Ch0 (WIO1) + * UMCA0, UMC30: Ch0 (WIO0) + */ + tmp = readl(SC_RSTCTRL4); + tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 | + SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 | + SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30; + writel(tmp, SC_RSTCTRL4); + readl(SC_RSTCTRL4); /* dummy read */ + + /* provide clocks */ + tmp = readl(SC_CLKCTRL4); + tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 | + SC_CLKCTRL4_CEN_UMC0; + writel(tmp, SC_CLKCTRL4); + readl(SC_CLKCTRL4); /* dummy read */ +} |