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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-10-27 14:47:02 (GMT) |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-10-29 08:24:26 (GMT) |
| commit | b8909976ed384c26a3bc3bbdb9a39feb8a73d396 (patch) | |
| tree | 03ea492b7ece2e5cdec9c0be6bf4ca9470091a3e /arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h | |
| parent | da0d4d138063aeeae1209998b55ff6909fd633d0 (diff) | |
| download | u-boot-fsl-qoriq-b8909976ed384c26a3bc3bbdb9a39feb8a73d396.tar.xz | |
ARM: uniphier: update DRAM init code for LD20 SoC (3rd)
- Constify UMC setting data arrays
- Merge data arrays *_d0 and *_d1.
- Add PHY parameters for LD20 C1 board
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h')
| -rw-r--r-- | arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h index 0c11b65..268ba7f 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h @@ -15,6 +15,7 @@ #define PHY_MAS_DLY_WIDTH 8 #define PHY_SCL_START (0x40 << (PHY_REG_SHIFT)) +#define PHY_SCL_START_GO_DONE BIT(28) #define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT)) #define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT)) #define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT)) |