Merge git://git.denx.de/u-boot-socfpga

7 files changed, 62 insertions, 0 deletions

diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi
index 5175f03..fa0bd7d 100644
--- a/arch/arm/dts/socfpga_arria5.dtsi
+++ b/arch/arm/dts/socfpga_arria5.dtsi
@@ -25,6 +25,8 @@
 			bus-width = <4>;
 			cap-mmc-highspeed;
 			cap-sd-highspeed;
+			drvsel = <3>;
+			smplsel = <0>;
 		};
 
 		sysmgr@ffd08000 {
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi
index de36209..040b236 100644
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -25,6 +25,8 @@
 			bus-width = <4>;
 			cap-mmc-highspeed;
 			cap-sd-highspeed;
+			drvsel = <3>;
+			smplsel = <0>;
 		};
 
 		sysmgr@ffd08000 {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 6782691..05b935d 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -19,6 +19,10 @@
 		device_type = "memory";
 		reg = <0x0 0x40000000>; /* 1GB */
 	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
 };
 
 &gmac1 {
@@ -37,6 +41,7 @@
 
 &mmc0 {
 	status = "okay";
+	u-boot,dm-pre-reloc;
 };
 
 &qspi {
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a413ea4..e4cc468 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_EBV_SOCRATES
+	bool "EBV SoCrates (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -38,11 +42,13 @@ config SYS_BOARD
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
@@ -55,5 +61,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 
 endif
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
new file mode 100644
index 0000000..a7056d4
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
+#define _SOCFPGA_A10_BASE_HARDWARE_H_
+
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS		0xff809000
+#define SOCFPGA_QSPIDATA_ADDRESS		0xffa00000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xffcfa000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS		0xffcfe400
+#define SOCFPGA_FPGAMGRREGS_ADDRESS		0xffd03000
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd06000
+#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS	0xffd07000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd07200
+#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS	0xffd07300
+#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS	0xffd07400
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_MPUSCU_ADDRESS			0xffffc000
+#define SOCFPGA_MPUL2_ADDRESS			0xfffff000
+#define SOCFPGA_I2C0_ADDRESS			0xffc02200
+#define SOCFPGA_I2C1_ADDRESS			0xffc02300
+
+#define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd05000
+
+#define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
+#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
+
+#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
index 6534283..6534283 100644
--- a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 666a2ef..e50fbd8 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -25,6 +25,7 @@ struct socfpga_reset_manager {
 	u32	per2_mod_reset;
 	u32	brg_mod_reset;
 	u32	misc_mod_reset;
+	u32	padding2[12];
 	u32	tstscratch;
 };