diff options
| author | Hadli, Manjunath <manjunath.hadli@ti.com> | 2012-02-06 00:30:43 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-12 09:11:32 (GMT) |
| commit | 6678cebc09226f9d34fb7e5e0631d0009689918b (patch) | |
| tree | b4f6c8d2c1f55db66495a87cddf676115e5766d1 /arch/arm | |
| parent | fd3d28e7a6be0e270bcd5b513355740bd89ed84d (diff) | |
| download | u-boot-fsl-qoriq-6678cebc09226f9d34fb7e5e0631d0009689918b.tar.xz | |
davinci: remove macro CONFIG_DISPLAY_CPUINFO
remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer
required. This is because clock info will be printed as part
'bdinfo' command and also remove support print_cpuinfo() as it will
no longer be called.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/cpu.c | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 9ea9785..1735555 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -115,21 +115,8 @@ int clk_get(enum davinci_clk_ids id) out: return pll_out; } -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) -{ - printf("Cores: ARM %d MHz", - clk_get(DAVINCI_ARM_CLKID) / 1000000); - printf("\nDDR: %d MHz\n", - /* DDR PHY uses an x2 input clock */ - clk_get(0x10001) / 1000000); - return 0; -} -#endif #else /* CONFIG_SOC_DA8XX */ -#ifdef CONFIG_DISPLAY_CPUINFO - static unsigned pll_div(volatile void *pllbase, unsigned offset) { u32 div; @@ -185,36 +172,6 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); } -int print_cpuinfo(void) -{ - /* REVISIT fetch and display CPU ID and revision information - * too ... that will matter as more revisions appear. - */ -#if defined(CONFIG_SOC_DM365) - printf("Cores: ARM %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV)); -#else - printf("Cores: ARM %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); -#endif - -#ifdef DSP_PLLDIV - printf(", DSP %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV)); -#endif - - printf("\nDDR: %d MHz\n", - /* DDR PHY uses an x2 input clock */ -#if defined(CONFIG_SOC_DM365) - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV) - / 2); -#else - pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) - / 2); -#endif - return 0; -} - #ifdef DAVINCI_DM6467EVM unsigned int davinci_arm_clk_get() { @@ -228,7 +185,6 @@ unsigned int davinci_clk_get(unsigned int div) return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; } #endif -#endif /* CONFIG_DISPLAY_CPUINFO */ #endif /* !CONFIG_SOC_DA8XX */ /* |