Merge git://git.denx.de/u-boot-rockchip

10 files changed, 140 insertions, 11 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 68d2791..ce34e3e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,12 +29,12 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3036-sdk.dtb \
+	rk3188-radxarock.dtb \
 	rk3288-evb.dtb \
 	rk3288-fennec.dtb \
 	rk3288-firefly.dtb \
 	rk3288-miqi.dtb \
 	rk3288-popmetal.dtb \
-	rk3188-radxarock.dtb \
 	rk3288-rock2-square.dtb \
 	rk3288-tinker.dtb \
 	rk3288-veyron-jerry.dtb \
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index c3a7ca2..e1f867b 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -30,6 +30,13 @@
 		status = "okay";
 	};
 
+	vccsys: vccsys {
+		compatible = "regulator-fixed";
+		regulator-name = "vccsys";
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	vcc3v3_sys: vcc3v3-sys {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_sys";
@@ -51,6 +58,7 @@
 		regulator-name = "vcc5v0_host";
 		gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 	};
+
 };
 
 &emmc_phy {
@@ -112,6 +120,37 @@
 	status = "okay";
 };
 
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+	i2c-scl-falling-time-ns = <50>;
+	i2c-scl-rising-time-ns = <100>;
+	u-boot,dm-pre-reloc;
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		clock-output-names = "xin32k", "wifibt_32kin";
+		interrupt-parent = <&gpio0>;
+		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		reg = <0x1b>;
+		rockchip,system-power-controller;
+		#clock-cells = <1>;
+		u-boot,dm-pre-reloc;
+		status = "okay";
+
+		vcc12-supply = <&vcc3v3_sys>;
+		regulators {
+			vcc33_lcd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc33_lcd";
+			};
+		};
+	};
+};
+
 &pinctrl {
 	pmic {
 		pmic_int_l: pmic-int-l {
diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts
index 917df1e..50e43c7 100644
--- a/arch/arm/dts/rk3399-puma.dts
+++ b/arch/arm/dts/rk3399-puma.dts
@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  *
- * SPDX-License-Identifier:     GPL-2.0+
+ * SPDX-License-Identifier:     GPL-2.0+	X11
  */
 
 /dts-v1/;
@@ -91,7 +91,6 @@
 &sdmmc {
         u-boot,dm-pre-reloc;
 	bus-width = <4>;
-	fifo-mode; /* until we fix DMA in SPL */
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index dbe55f2..d94d780 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -26,6 +26,7 @@
 		serial4 = &uart4;
 		mmc0 = &sdhci;
 		mmc1 = &sdmmc;
+		i2c0 = &i2c0;
 	};
 
 	cpus {
@@ -668,6 +669,21 @@
 		status = "disabled";
 	};
 
+	i2c0: i2c@ff3c0000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x0 0xff3c0000 0x0 0x1000>;
+		assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
+		assigned-clock-rates = <200000000>;
+		clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
+		clock-names = "i2c", "pclk";
+		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3399-pinctrl";
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index b340b05..c424753 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -337,6 +337,14 @@ enum {
 	GRF_GPIO2B4_SEL_MASK	= 3 << GRF_GPIO2B4_SEL_SHIFT,
 	GRF_SPI2TPM_CSN0	= 1,
 
+	/* GRF_GPIO2C_IOMUX */
+	GRF_GPIO2C0_SEL_SHIFT   = 0,
+	GRF_GPIO2C0_SEL_MASK    = 3 << GRF_GPIO2C0_SEL_SHIFT,
+	GRF_UART0BT_SIN         = 1,
+	GRF_GPIO2C1_SEL_SHIFT   = 2,
+	GRF_GPIO2C1_SEL_MASK    = 3 << GRF_GPIO2C1_SEL_SHIFT,
+	GRF_UART0BT_SOUT        = 1,
+
 	/* GRF_GPIO3A_IOMUX */
 	GRF_GPIO3A0_SEL_SHIFT   = 0,
 	GRF_GPIO3A0_SEL_MASK    = 3 << GRF_GPIO3A0_SEL_SHIFT,
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index af0796d..2b752ad 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -18,6 +18,7 @@ config ROCKCHIP_RK3188
 	select SUPPORT_TPL
 	select SPL
 	select TPL
+	select BOARD_LATE_INIT
 	select ROCKCHIP_BROM_HELPER
 	help
 	  The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
@@ -55,6 +56,7 @@ config ROCKCHIP_RK3399
 	select SPL
 	select SPL_SEPARATE_BSS
 	select ENABLE_ARM_SOC_BOOT0_HOOK
+	select DEBUG_UART_BOARD_INIT
 	help
 	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
 	  and quad-core Cortex-A53.
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index c370156..4be711e 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -11,6 +11,7 @@
 #include <syscon.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3188.h>
 #include <asm/arch/periph.h>
 #include <asm/arch/pmu_rk3288.h>
 #include <asm/arch/boot_mode.h>
@@ -19,6 +20,23 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_late_init(void)
+{
+	struct rk3188_grf *grf;
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(grf)) {
+		error("grf syscon returned %ld\n", PTR_ERR(grf));
+	} else {
+		/* enable noc remap to mimic legacy loaders */
+		rk_clrsetreg(&grf->soc_con0,
+			NOC_REMAP_MASK << NOC_REMAP_SHIFT,
+			NOC_REMAP_MASK << NOC_REMAP_SHIFT);
+	}
+
+	return 0;
+}
+
 int board_init(void)
 {
 #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 4f84ec1..050f5e1 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -156,19 +156,24 @@ void secure_timer_init(void)
 	writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
 }
 
-#define GRF_EMMCCORE_CON11 0xff77f02c
-void board_init_f(ulong dummy)
-{
-	struct udevice *pinctrl;
-	struct udevice *dev;
-	int ret;
+#define SGRF_DDR_RGN_CON16 0xff330040
 
-	/* Example code showing how to enable the debug UART on RK3288 */
+void board_debug_uart_init(void)
+{
 #include <asm/arch/grf_rk3399.h>
-	/* Enable early UART2 channel C on the RK3399 */
 #define GRF_BASE	0xff770000
 	struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
 
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+	/* Enable early UART0 on the RK3399 */
+	rk_clrsetreg(&grf->gpio2c_iomux,
+		     GRF_GPIO2C0_SEL_MASK,
+		     GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
+	rk_clrsetreg(&grf->gpio2c_iomux,
+		     GRF_GPIO2C1_SEL_MASK,
+		     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#else
+	/* Enable early UART2 channel C on the RK3399 */
 	rk_clrsetreg(&grf->gpio4c_iomux,
 		     GRF_GPIO4C3_SEL_MASK,
 		     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
@@ -179,6 +184,16 @@ void board_init_f(ulong dummy)
 	rk_clrsetreg(&grf->soc_con7,
 		     GRF_UART_DBG_SEL_MASK,
 		     GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
+#endif
+}
+
+#define GRF_EMMCCORE_CON11 0xff77f02c
+void board_init_f(ulong dummy)
+{
+	struct udevice *pinctrl;
+	struct udevice *dev;
+	int ret;
+
 #define EARLY_UART
 #ifdef EARLY_UART
 	/*
@@ -201,6 +216,17 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	/*
+	 * Disable DDR security regions.
+	 *
+	 * As we are entered from the BootROM, the region from
+	 * 0x0 through 0xfffff (i.e. the first MB of memory) will
+	 * be protected. This will cause issues with the DW_MMC
+	 * driver, which tries to DMA from/to the stack (likely)
+	 * located in this range.
+	 */
+	rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
+
 	secure_timer_init();
 
 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
@@ -238,6 +264,7 @@ void spl_board_init(void)
 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
 	back_to_bootrom();
 #endif
+
 	return;
 err:
 	printf("spl_board_init: Error %d\n", ret);
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 83bd04a..415466a 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -10,6 +10,24 @@ config TARGET_EVB_RK3399
 	  with full function and phisical connectors support like type-C ports,
 	  usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
 
+config TARGET_PUMA_RK3399
+	bool "Theobroma Systems RK3399-Q7 (Puma)"
+	help
+	  The RK3399-Q7 (Puma) is a system-on-module (designed and
+	  marketed by Theobroma Systems) featuring the Rockchip RK3399
+	  in a Qseven-compatible form-factor (running of a single 5V
+	  supply and exposing its external interfaces on a MXM-230
+	  connector).
+
+	  Key features of the RK3399-Q7 include:
+	   * on-module USB 3.0 hub (2x USB 3.0 host + 1x USB 2.0 host)
+	   * USB 3.0 dual-role
+	   * on-module Micrel KSZ9031 GbE PHY
+	   * on-module eMMC (up to 256GB configurations available)
+	   * on-module DDR3 (1GB, 2GB and 4GB configurations available)
+	   * HDMI, eDP, MIPI-DSI, MIPI-DSI/CSI and MIPI-CSI
+	   * SPI, I2C, I2S, UART, GPIO, ...
+
 endchoice
 
 config SYS_SOC
@@ -19,5 +37,6 @@ config SYS_MALLOC_F_LEN
 	default 0x0800
 
 source "board/rockchip/evb_rk3399/Kconfig"
+source "board/theobroma-systems/puma_rk3399/Kconfig"
 
 endif
diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
index d32985b..74d4552 100644
--- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
@@ -14,6 +14,7 @@ static const struct udevice_id rk3399_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
 	{ .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
 	{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
+	{ }
 };
 
 U_BOOT_DRIVER(syscon_rk3399) = {