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authorTom Rini <trini@ti.com>2013-04-10 13:10:54 (GMT)
committerTom Rini <trini@ti.com>2013-04-10 14:04:40 (GMT)
commitb996a3e9a88ce247bce3d29a9ac5ff34c37845fd (patch)
tree9afd1eb400a01c7d46fcb61b81c7186e8772c0d9 /arch/arm
parent74f40ea1bcbe96a91067d6f8056a18393d311e67 (diff)
downloadu-boot-fsl-qoriq-b996a3e9a88ce247bce3d29a9ac5ff34c37845fd.tar.xz
am335x: Update timings for the beaglebone again
After further testing we can run DDR at 400MHz so update the timings again. Tested-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 260cc34..914df01 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -84,19 +84,19 @@
#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
/* Micron MT41K256M16HA-125E */
-#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100006
-#define MT41K256M16HA125E_EMIF_TIM1 0x0888A39B
-#define MT41K256M16HA125E_EMIF_TIM2 0x26517FDA
-#define MT41K256M16HA125E_EMIF_TIM3 0x501F84EF
-#define MT41K256M16HA125E_EMIF_SDCFG 0x61C04BB2
-#define MT41K256M16HA125E_EMIF_SDREF 0x0000093B
+#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
+#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2 0x26437FDA
+#define MT41K256M16HA125E_EMIF_TIM3 0x501F83FF
+#define MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2
+#define MT41K256M16HA125E_EMIF_SDREF 0xC30
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
-#define MT41K256M16HA125E_RATIO 0x40
+#define MT41K256M16HA125E_RATIO 0x80
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
-#define MT41K256M16HA125E_RD_DQS 0x3C
-#define MT41K256M16HA125E_WR_DQS 0x45
-#define MT41K256M16HA125E_PHY_WR_DATA 0x7F
+#define MT41K256M16HA125E_RD_DQS 0x3A
+#define MT41K256M16HA125E_WR_DQS 0x42
+#define MT41K256M16HA125E_PHY_WR_DATA 0x7E
#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B