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authorAneesh V <aneesh@ti.com>2011-12-29 08:47:17 (GMT)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-01-16 07:40:11 (GMT)
commitfe7104b307a12f0d5f02526bea00162d95589616 (patch)
treef8fa28a6668326d6de9aeaccc69ffb587ec547a1 /arch/arm
parent6cce55047c4c7687868367832f0e42aeda0d63f2 (diff)
downloadu-boot-fsl-qoriq-fe7104b307a12f0d5f02526bea00162d95589616.tar.xz
omap4: fix boot issue on ES2.0 Panda
Fix boot issue on ES2.0 Panda by tuning some IO settings. The CONTROL_EFUSE_2 register has to be over-ridden in software for 4430 boards. Commit 23e9f0723e48615332119de4f4ec7a833a282628 wrongly did this for CONTROL_EFUSE_1. Reverting this and doing it for CONTROL_EFUSE_2. Signed-off-by: Aneesh V <aneesh@ti.com> Tested-by: Raúl Porcel <armin76@gentoo.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/omap4/hwinit.c4
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index 37a86b4..91f8320 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -110,10 +110,10 @@ void do_io_settings(void)
* i. unconditionally for all 4430
* ii. only if un-trimmed for 4460
*/
- if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_1))
+ if (!readl(&ctrl->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
- if (!readl(&ctrl->control_efuse_2))
+ if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
}
#endif
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 4d8c89f..416c6de 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -116,7 +116,7 @@
#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
-#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
+#define CONTROL_EFUSE_2_OVERRIDE 0x99084000
/* LPDDR2 IO regs */
#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C