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| author | Tom Rini <trini@ti.com> | 2012-10-17 15:57:13 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-17 15:57:13 (GMT) |
| commit | d1ff690612415470a681787c029803952142043d (patch) | |
| tree | 09a7a42be56797aa57abefc8f464bffa1ecb16da /arch/mips/cpu/mips32 | |
| parent | ff04f6d1224d8952b566b8671222151495883073 (diff) | |
| parent | 6b2eba1b7cd661fc6b2b0e0d4d039d1c299e2e07 (diff) | |
| download | u-boot-fsl-qoriq-d1ff690612415470a681787c029803952142043d.tar.xz | |
Merge branch 'master' of git://git.denx.de/u-boot-mips
Diffstat (limited to 'arch/mips/cpu/mips32')
| -rw-r--r-- | arch/mips/cpu/mips32/cache.S | 10 | ||||
| -rw-r--r-- | arch/mips/cpu/mips32/cpu.c | 8 |
2 files changed, 9 insertions, 9 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index e683e8b..64dfad0 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -85,17 +85,17 @@ LEAF(mips_init_icache) /* clear tag to invalidate */ PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, a1 -1: cache_op Index_Store_Tag_I t0 +1: cache_op INDEX_STORE_TAG_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE -2: cache_op Fill t0 +2: cache_op FILL t0 PTR_ADDU t0, a2 bne t0, t1, 2b /* invalidate again - prudent but not strictly neccessary */ PTR_LI t0, INDEX_BASE -1: cache_op Index_Store_Tag_I t0 +1: cache_op INDEX_STORE_TAG_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b 9: jr ra @@ -110,7 +110,7 @@ LEAF(mips_init_dcache) /* clear all tags */ PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, a1 -1: cache_op Index_Store_Tag_D t0 +1: cache_op INDEX_STORE_TAG_D t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* load from each line (in cached space) */ @@ -120,7 +120,7 @@ LEAF(mips_init_dcache) bne t0, t1, 2b /* clear all tags */ PTR_LI t0, INDEX_BASE -1: cache_op Index_Store_Tag_D t0 +1: cache_op INDEX_STORE_TAG_D t0 PTR_ADDU t0, a2 bne t0, t1, 1b 9: jr ra diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c index 7b49e1b..50bb248 100644 --- a/arch/mips/cpu/mips32/cpu.c +++ b/arch/mips/cpu/mips32/cpu.c @@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size) return; while (1) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_INVALIDATE_I, addr); if (addr == aend) break; addr += lsize; @@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); while (1) { - cache_op(Hit_Writeback_Inv_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); if (addr == aend) break; addr += lsize; @@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); while (1) { - cache_op(Hit_Invalidate_D, addr); + cache_op(HIT_INVALIDATE_D, addr); if (addr == aend) break; addr += lsize; |