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| author | Marek Vasut <marex@denx.de> | 2012-08-12 14:53:35 (GMT) |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2012-08-17 18:13:48 (GMT) |
| commit | 36d0a42b682e4d8493e8c080425bc9fb6f188cd2 (patch) | |
| tree | 1018aeebdd189000662df68dfada0e28d92f48b4 /arch/mips/cpu/xburst | |
| parent | e66443fdb5355e68cfdbbdd37248c4b7eb4968f5 (diff) | |
| download | u-boot-fsl-qoriq-36d0a42b682e4d8493e8c080425bc9fb6f188cd2.tar.xz | |
dm: mips: Fix lb60 WDT control
Write the TSCR register via 32bit write instead of 16bit one.
The register is 32bit wide and bit 16 is being set, triggering
gcc overflow error and making the code broken.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel <zpxu@ingenic.cn>
Cc: Shinya Kuribayashi <skuribay@pobox.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
Diffstat (limited to 'arch/mips/cpu/xburst')
| -rw-r--r-- | arch/mips/cpu/xburst/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c index e976341..ddcbfaa 100644 --- a/arch/mips/cpu/xburst/cpu.c +++ b/arch/mips/cpu/xburst/cpu.c @@ -62,7 +62,7 @@ void __attribute__((weak)) _machine_restart(void) writew(100, &wdt->tdr); /* wdt_set_data(100) */ writew(0, &wdt->tcnt); /* wdt_set_count(0); */ - writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ + writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */ while (1) |