diff options
| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:15 (GMT) |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 19:31:19 (GMT) |
| commit | d1001e3f0ce0059a55a870c42bac8aba2e4befec (patch) | |
| tree | bb8dd7437496f9705ab0dbd59460ed3ce60a57f4 /arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | |
| parent | fd3cebd020edad5fa18ff5a64cde3aa75aa896c8 (diff) | |
| download | u-boot-fsl-qoriq-d1001e3f0ce0059a55a870c42bac8aba2e4befec.tar.xz | |
powerpc/corenet2: Add SerDes for corenet2
Create new files to handle 2nd generation Chassis as the registers are
organized differently.
- Add SerDes protocol parsing and detection
- Add support of 4 SerDes
- Add CPRI protocol in fsl_serdes.h
The Common Public Radio Interface (CPRI) is publicly available
specification that standardizes the protocol interface between the
radio equipment control (REC) and the radio equipment (RE) in wireless
basestations. This allows interoperability of equipment from different
vendors,and preserves the software investment made by wireless service
providers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h index c82060d..3c551e9 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -22,14 +22,6 @@ #ifndef __FSL_CORENET_SERDES_H #define __FSL_CORENET_SERDES_H -/* - * Note: For P5040, the fourth SerDes bank is on SerDes2, but U-boot currently - * only supports one SerDes controller. For now, pretend that we have three - * banks and 18 lanes on the P5040. - */ -#define SRDS_MAX_LANES 18 -#define SRDS_MAX_BANK 3 - enum srds_bank { FSL_SRDS_BANK_1 = 0, FSL_SRDS_BANK_2 = 1, |