diff options
| author | Simon Glass <sjg@chromium.org> | 2017-03-28 16:27:21 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-04-05 17:52:51 (GMT) |
| commit | 26345552d65f9891879d62b0b0a427716f0e662b (patch) | |
| tree | 4c8ce8e38164fd812d1504b590493b5211d2003d /arch/powerpc/cpu | |
| parent | d593c61672eb0fe21380750b3b1a816cea9f86bd (diff) | |
| download | u-boot-fsl-qoriq-26345552d65f9891879d62b0b0a427716f0e662b.tar.xz | |
board_f: Remove sdram_adjust_866() from the init sequence
We can just call this from the only function that needs it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xx/speed.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index 613209c..7a532cc 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -237,6 +237,21 @@ int get_clocks (void) static long init_pll_866 (long clk); +/* Adjust sdram refresh rate to actual CPU clock. + */ +static int sdram_adjust_866(void) +{ + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + long mamr; + + mamr = immr->im_memctl.memc_mamr; + mamr &= ~MAMR_PTA_MSK; + mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); + immr->im_memctl.memc_mamr = mamr; + + return 0; +} + /* This function sets up PLL (init_pll_866() is called) and * fills gd->cpu_clk and gd->bus_clk according to the environment * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk' @@ -278,22 +293,7 @@ int get_clocks(void) } immr->im_clkrst.car_sccr = sccr_reg; - return (0); -} - -/* Adjust sdram refresh rate to actual CPU clock. - */ -int sdram_adjust_866 (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - long mamr; - - mamr = immr->im_memctl.memc_mamr; - mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); - immr->im_memctl.memc_mamr = mamr; - - return (0); + return sdram_adjust_866(); } /* Configure PLL for MPC866/859/885 CPU series |