diff options
| author | Simon Glass <sjg@chromium.org> | 2017-03-28 16:27:22 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-04-05 17:52:52 (GMT) |
| commit | 75efc34bfa80dff27f98d8ce13237fba4c54ea8f (patch) | |
| tree | 004d52e91a07f644ea84901d85d38c0778bb4ae3 /arch/powerpc/cpu | |
| parent | 26345552d65f9891879d62b0b0a427716f0e662b (diff) | |
| download | u-boot-fsl-qoriq-75efc34bfa80dff27f98d8ce13237fba4c54ea8f.tar.xz | |
board_f: Remove adjust_sdram_tbs_8xx() from the init sequence
We can just call this from the only place that needs it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc8xx/speed.c | 63 |
1 files changed, 33 insertions, 30 deletions
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index 7a532cc..e2295d2 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -252,6 +252,33 @@ static int sdram_adjust_866(void) return 0; } +/* + * Adjust sdram refresh rate to actual CPU clock + * and set timebase source according to actual CPU clock + */ +static int adjust_sdram_tbs_8xx(void) +{ +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) && \ + !defined(CONFIG_TQM885D) + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + long mamr; + long sccr; + + mamr = immr->im_memctl.memc_mamr; + mamr &= ~MAMR_PTA_MSK; + mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); + immr->im_memctl.memc_mamr = mamr; + + if (gd->cpu_clk < 67000000) { + sccr = immr->im_clkrst.car_sccr; + sccr |= SCCR_TBS; + immr->im_clkrst.car_sccr = sccr; + } +#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ + + return 0; +} + /* This function sets up PLL (init_pll_866() is called) and * fills gd->cpu_clk and gd->bus_clk according to the environment * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk' @@ -264,6 +291,7 @@ int get_clocks(void) char tmp[64]; long cpuclk = 0; long sccr_reg; + int ret; if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; @@ -293,7 +321,11 @@ int get_clocks(void) } immr->im_clkrst.car_sccr = sccr_reg; - return sdram_adjust_866(); + ret = sdram_adjust_866(); + if (ret) + return ret; + + return adjust_sdram_tbs_8xx(); } /* Configure PLL for MPC866/859/885 CPU series @@ -369,32 +401,3 @@ static long init_pll_866 (long clk) } #endif /* CONFIG_8xx_CPUCLK_DEFAULT */ - -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ - && !defined(CONFIG_TQM885D) -/* - * Adjust sdram refresh rate to actual CPU clock - * and set timebase source according to actual CPU clock - */ -int adjust_sdram_tbs_8xx (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - long mamr; - long sccr; - - mamr = immr->im_memctl.memc_mamr; - mamr &= ~MAMR_PTA_MSK; - mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); - immr->im_memctl.memc_mamr = mamr; - - if (gd->cpu_clk < 67000000) { - sccr = immr->im_clkrst.car_sccr; - sccr |= SCCR_TBS; - immr->im_clkrst.car_sccr = sccr; - } - - return (0); -} -#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ - -/* ------------------------------------------------------------------------- */ |