diff options
| author | Evert Pap <evert.pap@sintecs.nl> | 2016-03-31 13:54:38 (GMT) |
|---|---|---|
| committer | vojo <joris.van.vossen@sintecs.nl> | 2017-08-23 08:06:41 (GMT) |
| commit | a5deb669f027575829326eb5f07e8a47bc870005 (patch) | |
| tree | e5ad6cf8e5e5c4712c0797e9af08f2b84a5831e0 /arch/powerpc/include/asm/mpc8xxx_gpio.h | |
| parent | bc5d0384458466ed5b3608d326eec03cd4f13016 (diff) | |
| download | u-boot-fsl-qoriq-a5deb669f027575829326eb5f07e8a47bc870005.tar.xz | |
dm: gpio: Add DM GPIO driver for MPC8xxx platforms
This driver adds DM GPIO support for the NXP QorIQ T10xx series.
ported from the linux kernel 4.5
* (b562e44f507e863c6792946e4e1b1449fbbac85d)
* and removed the interrupt functionallity.
This driver could also support the older platforms, as well as the new
LayerScape (ARM) based platforms, but these platforms are not
supported at this time.
Diffstat (limited to 'arch/powerpc/include/asm/mpc8xxx_gpio.h')
| -rw-r--r-- | arch/powerpc/include/asm/mpc8xxx_gpio.h | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mpc8xxx_gpio.h b/arch/powerpc/include/asm/mpc8xxx_gpio.h new file mode 100644 index 0000000..d4a5b7c --- /dev/null +++ b/arch/powerpc/include/asm/mpc8xxx_gpio.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2016 Scalys B.V. <u-boot@scalys.com> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _POWERPC_ASM_MPC8XXX_GPIO_H +#define _POWERPC_ASM_MPC8XXX_GPIO_H + +#define MPC8XXX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) +#define MPC8XXX_GPIO_TO_PORT(gpio) (gpio/32) +#define MPC8XXX_GPIO_TO_PIN(gpio) (gpio&31) + +static inline void mpc8xxx_gpio_set(uint32_t gpio, int value) +{ + int port, pin; + ccsr_gpio_t *gpio_regs; + uint32_t regval; + + port = MPC8XXX_GPIO_TO_PORT(gpio); + pin = MPC8XXX_GPIO_TO_PIN(gpio); + + switch (port) { +#ifdef CONFIG_SYS_MPC8XXX_GPIO1_ADDR + case 0: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO1_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO2_ADDR + case 1: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO2_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO3_ADDR + case 2: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO3_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO4_ADDR + case 3: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO4_ADDR; + break; +#endif + default: + return; + } + + /* Set output */ + regval = in_be32(&(gpio_regs->gpdat)); + regval |= (0x80000000 >> pin); + out_be32(&(gpio_regs->gpdat), regval); + + /* Set direction to acivate gpio pin */ + regval = in_be32(&(gpio_regs->gpdir)); + regval |= (0x80000000 >> pin); + out_be32(&(gpio_regs->gpdir), regval); +} + +static inline int mpc8xxx_gpio_get(uint32_t gpio, int value) +{ + int port, pin; + ccsr_gpio_t *gpio_regs; + uint32_t regval; + + port = MPC8XXX_GPIO_TO_PORT(gpio); + pin = MPC8XXX_GPIO_TO_PIN(gpio); + + switch (port) { +#ifdef CONFIG_SYS_MPC8XXX_GPIO1_ADDR + case 0: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO1_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO2_ADDR + case 1: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO2_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO3_ADDR + case 2: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO3_ADDR; + break; +#endif +#ifdef CONFIG_SYS_MPC8XXX_GPIO4_ADDR + case 3: + gpio_regs = (ccsr_gpio_t *) CONFIG_SYS_MPC8XXX_GPIO4_ADDR; + break; +#endif + default: + return; + } + + /* Get inputs */ + regval = in_be32(&(gpio_regs->gpdat)); + regval <<= pin; + regval &= 1; + + return regval; +} + +#endif /* _POWERPC_ASM_MPC8XXX_GPIO_H */ |