diff options
author | York Sun <yorksun@freescale.com> | 2013-04-01 18:29:11 (GMT) |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2013-04-01 20:33:52 (GMT) |
commit | 472d546054dadacca91530bad42ad06f6408124e (patch) | |
tree | 3acfccea2d15c21f12651a852d31452d33ea98e0 /arch/powerpc | |
parent | 5644369450635fa5c2967bee55b1ac41f6e988d0 (diff) | |
download | u-boot-fsl-qoriq-472d546054dadacca91530bad42ad06f6408124e.tar.xz |
Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.
All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.
Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c | 71 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 201 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c | 15 |
4 files changed, 138 insertions, 151 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 5495dc5..825a292 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -513,7 +513,7 @@ void fsl_serdes_init(void) size_t arglen; #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 - int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ + int need_serdes_a001; /* true == need work-around for SERDES A001 */ #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 char buffer[HWCONFIG_BUFFER_SIZE]; diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c index 8a20a2b..161d274 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c @@ -88,8 +88,6 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")) #define NUMMEMTESTS 8 #define NUMMEMWORDS 8 #define MAXBXCR 4 -#define TRUE 1 -#define FALSE 0 /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory @@ -298,7 +296,7 @@ static void get_spd_info(unsigned long *dimm_populated, unsigned char num_of_bytes; unsigned char total_size; - dimm_found = FALSE; + dimm_found = false; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { num_of_bytes = 0; total_size = 0; @@ -307,16 +305,16 @@ static void get_spd_info(unsigned long *dimm_populated, total_size = spd_read(iic0_dimm_addr[dimm_num], 1); if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; + dimm_populated[dimm_num] = true; + dimm_found = true; debug("DIMM slot %lu: populated\n", dimm_num); } else { - dimm_populated[dimm_num] = FALSE; + dimm_populated[dimm_num] = false; debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); spd_ddr_init_hang (); } @@ -330,7 +328,7 @@ static void check_mem_type(unsigned long *dimm_populated, unsigned char dimm_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); switch (dimm_type) { case 7: @@ -356,7 +354,7 @@ static void check_volt_type(unsigned long *dimm_populated, unsigned long voltage_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); if (voltage_type != 0x04) { printf("ERROR: DIMM %lu with unsupported voltage level.\n", @@ -398,12 +396,12 @@ static void program_cfg0(unsigned long *dimm_populated, /* * FIXME: assume the DDR SDRAMs in both banks are the same */ - ecc_enabled = TRUE; + ecc_enabled = true; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { ecc = spd_read(iic0_dimm_addr[dimm_num], 11); if (ecc != 0x02) { - ecc_enabled = FALSE; + ecc_enabled = false; } /* @@ -437,7 +435,7 @@ static void program_cfg0(unsigned long *dimm_populated, /* * program Memory Data Error Checking */ - if (ecc_enabled == TRUE) { + if (ecc_enabled == true) { cfg0 |= SDRAM_CFG0_MCHK_GEN; } else { cfg0 |= SDRAM_CFG0_MCHK_NON; @@ -493,7 +491,7 @@ static void program_rtr(unsigned long *dimm_populated, bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); switch (refresh_rate_type) { case 0x00: @@ -585,15 +583,15 @@ static void program_tr0(unsigned long *dimm_populated, t_rp_ns = 0; t_rcd_ns = 0; t_ras_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; + cas_2_0_available = true; + cas_2_5_available = true; + cas_3_0_available = true; tcyc_2_0_ns_x_10 = 0; tcyc_2_5_ns_x_10 = 0; tcyc_3_0_ns_x_10 = 0; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; @@ -640,7 +638,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_3_0_available = FALSE; + cas_3_0_available = false; } if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { @@ -650,7 +648,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_2_5_available = FALSE; + cas_2_5_available = false; } if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { @@ -660,7 +658,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_2_0_available = FALSE; + cas_2_0_available = false; } break; @@ -683,13 +681,13 @@ static void program_tr0(unsigned long *dimm_populated, /* * Program SD_CASL field */ - if ((cas_2_0_available == TRUE) && + if ((cas_2_0_available == true) && (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_2_0_CLK; - } else if ((cas_2_5_available == TRUE) && + } else if ((cas_2_5_available == true) && (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_2_5_CLK; - } else if ((cas_3_0_available == TRUE) && + } else if ((cas_3_0_available == true) && (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_3_0_CLK; } else { @@ -950,9 +948,9 @@ static void program_tr1(void) current_fail_length = 0; current_start = 0; rdclt_offset = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; + window_found = false; + fail_found = false; + pass_found = false; debug("Starting memory test "); for (k = 0; k < NUMHALFCYCLES; k++) { @@ -963,8 +961,8 @@ static void program_tr1(void) mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) { current_start = rdclt_offset + rdclt; } @@ -983,10 +981,10 @@ static void program_tr1(void) current_fail_length++; if (current_fail_length >= (dly_val>>2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; + if (fail_found == false) { + fail_found = true; + } else if (pass_found == true) { + window_found = true; break; } } @@ -994,9 +992,8 @@ static void program_tr1(void) } debug("."); - if (window_found == TRUE) { + if (window_found == true) break; - } tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; rdclt_offset += dly_val; @@ -1006,7 +1003,7 @@ static void program_tr1(void) /* * make sure we find the window */ - if (window_found == FALSE) { + if (window_found == false) { printf("ERROR: Cannot determine a common read delay.\n"); spd_ddr_init_hang (); } @@ -1115,7 +1112,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, bank_base_addr = CONFIG_SYS_SDRAM_BASE; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 85217ea..def7ebf 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -241,13 +241,6 @@ void board_add_ram_info(int use_default) /*-----------------------------------------------------------------------------+ * Defines *-----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #define SDRAM_DDR1 1 #define SDRAM_DDR2 2 #define SDRAM_NONE 0 @@ -683,7 +676,7 @@ static void get_spd_info(unsigned long *dimm_populated, unsigned char num_of_bytes; unsigned char total_size; - dimm_found = FALSE; + dimm_found = false; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { num_of_bytes = 0; total_size = 0; @@ -696,16 +689,16 @@ static void get_spd_info(unsigned long *dimm_populated, iic0_dimm_addr[dimm_num], total_size); if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; + dimm_populated[dimm_num] = true; + dimm_found = true; debug("DIMM slot %lu: populated\n", dimm_num); } else { - dimm_populated[dimm_num] = FALSE; + dimm_populated[dimm_num] = false; debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); spd_ddr_init_hang (); } @@ -724,7 +717,7 @@ static void check_mem_type(unsigned long *dimm_populated, unsigned long dimm_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); switch (dimm_type) { case 1: @@ -994,14 +987,14 @@ static void program_copt1(unsigned long *dimm_populated, unsigned long val; #ifdef CONFIG_DDR_ECC - ecc_enabled = TRUE; + ecc_enabled = true; #else - ecc_enabled = FALSE; + ecc_enabled = false; #endif - dimm_32bit = FALSE; - dimm_64bit = FALSE; - buf0 = FALSE; - buf1 = FALSE; + dimm_32bit = false; + dimm_64bit = false; + buf0 = false; + buf1 = false; /*------------------------------------------------------------------ * Set memory controller options reg 1, SDRAM_MCOPT1. @@ -1026,7 +1019,7 @@ static void program_copt1(unsigned long *dimm_populated, /* test ecc support */ ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11); if (ecc != 0x02) /* ecc not supported */ - ecc_enabled = FALSE; + ecc_enabled = false; /* test bank count */ bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17); @@ -1048,15 +1041,15 @@ static void program_copt1(unsigned long *dimm_populated, if (registered == 1) { /* DDR2 always buffered */ /* TODO: what about above comments ? */ mcopt1 |= SDRAM_MCOPT1_RDEN; - buf0 = TRUE; + buf0 = true; } else { /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */ if ((attribute & 0x02) == 0x00) { /* buffered not supported */ - buf0 = FALSE; + buf0 = false; } else { mcopt1 |= SDRAM_MCOPT1_RDEN; - buf0 = TRUE; + buf0 = true; } } } @@ -1068,14 +1061,14 @@ static void program_copt1(unsigned long *dimm_populated, if (registered == 1) { /* DDR2 always buffered */ mcopt1 |= SDRAM_MCOPT1_RDEN; - buf1 = TRUE; + buf1 = true; } else { if ((attribute & 0x02) == 0x00) { /* buffered not supported */ - buf1 = FALSE; + buf1 = false; } else { mcopt1 |= SDRAM_MCOPT1_RDEN; - buf1 = TRUE; + buf1 = true; } } } @@ -1087,11 +1080,11 @@ static void program_copt1(unsigned long *dimm_populated, switch (data_width) { case 72: case 64: - dimm_64bit = TRUE; + dimm_64bit = true; break; case 40: case 32: - dimm_32bit = TRUE; + dimm_32bit = true; break; default: printf("WARNING: Detected a DIMM with a data width of %lu bits.\n", @@ -1110,20 +1103,19 @@ static void program_copt1(unsigned long *dimm_populated, } } - if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) { + if ((dimm_64bit == true) && (dimm_32bit == true)) { printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n"); spd_ddr_init_hang (); - } - else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) { + } else if ((dimm_64bit == true) && (dimm_32bit == false)) { mcopt1 |= SDRAM_MCOPT1_DMWD_64; - } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) { + } else if ((dimm_64bit == false) && (dimm_32bit == true)) { mcopt1 |= SDRAM_MCOPT1_DMWD_32; } else { printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n"); spd_ddr_init_hang (); } - if (ecc_enabled == TRUE) + if (ecc_enabled == true) mcopt1 |= SDRAM_MCOPT1_MCHK_GEN; else mcopt1 |= SDRAM_MCOPT1_MCHK_NON; @@ -1171,14 +1163,14 @@ static void program_codt(unsigned long *dimm_populated, total_rank += dimm_rank; total_dimm++; if ((dimm_num == 0) && (total_dimm == 1)) - firstSlot = TRUE; + firstSlot = true; else - firstSlot = FALSE; + firstSlot = false; } } if (dimm_type == SDRAM_DDR2) { codt |= SDRAM_CODT_DQS_1_8_V_DDR2; - if ((total_dimm == 1) && (firstSlot == TRUE)) { + if ((total_dimm == 1) && (firstSlot == true)) { if (total_rank == 1) { /* PUUU */ codt |= CALC_ODT_R(0); modt0 = CALC_ODT_W(0); @@ -1193,7 +1185,7 @@ static void program_codt(unsigned long *dimm_populated, modt2 = 0x00000000; modt3 = 0x00000000; } - } else if ((total_dimm == 1) && (firstSlot != TRUE)) { + } else if ((total_dimm == 1) && (firstSlot != true)) { if (total_rank == 1) { /* UUPU */ codt |= CALC_ODT_R(2); modt0 = 0x00000000; @@ -1467,26 +1459,26 @@ static void program_mode(unsigned long *dimm_populated, * the dimm modules installed. *-----------------------------------------------------------------*/ t_wr_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; - cas_4_0_available = TRUE; - cas_5_0_available = TRUE; + cas_2_0_available = true; + cas_2_5_available = true; + cas_3_0_available = true; + cas_4_0_available = true; + cas_5_0_available = true; max_2_0_tcyc_ns_x_100 = 10; max_2_5_tcyc_ns_x_100 = 10; max_3_0_tcyc_ns_x_100 = 10; max_4_0_tcyc_ns_x_100 = 10; max_5_0_tcyc_ns_x_100 = 10; - sdram_ddr1 = TRUE; + sdram_ddr1 = true; /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) { if (dimm_populated[dimm_num] == SDRAM_DDR1) - sdram_ddr1 = TRUE; + sdram_ddr1 = true; else - sdram_ddr1 = FALSE; + sdram_ddr1 = false; cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit); @@ -1543,7 +1535,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_4_0_available = FALSE; + cas_4_0_available = false; } if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && @@ -1554,7 +1546,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_3_0_available = FALSE; + cas_3_0_available = false; } if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && @@ -1565,7 +1557,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_2_5_available = FALSE; + cas_2_5_available = false; } if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && @@ -1576,7 +1568,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_2_0_available = FALSE; + cas_2_0_available = false; } } else { /* @@ -1592,7 +1584,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_5_0_available = FALSE; + cas_5_0_available = false; } if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && @@ -1603,7 +1595,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_4_0_available = FALSE; + cas_4_0_available = false; } if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && @@ -1614,7 +1606,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_3_0_available = FALSE; + cas_3_0_available = false; } } } @@ -1636,14 +1628,17 @@ static void program_mode(unsigned long *dimm_populated, debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk); debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk); - if (sdram_ddr1 == TRUE) { /* DDR1 */ - if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) { + if (sdram_ddr1 == true) { /* DDR1 */ + if ((cas_2_0_available == true) && + (sdram_freq <= cycle_2_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK; *selected_cas = DDR_CAS_2; - } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) { + } else if ((cas_2_5_available == true) && + (sdram_freq <= cycle_2_5_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK; *selected_cas = DDR_CAS_2_5; - } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { + } else if ((cas_3_0_available == true) && + (sdram_freq <= cycle_3_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK; *selected_cas = DDR_CAS_3; } else { @@ -1656,13 +1651,16 @@ static void program_mode(unsigned long *dimm_populated, debug("cas_3_0_available=%d\n", cas_3_0_available); debug("cas_4_0_available=%d\n", cas_4_0_available); debug("cas_5_0_available=%d\n", cas_5_0_available); - if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { + if ((cas_3_0_available == true) && + (sdram_freq <= cycle_3_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK; *selected_cas = DDR_CAS_3; - } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) { + } else if ((cas_4_0_available == true) && + (sdram_freq <= cycle_4_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK; *selected_cas = DDR_CAS_4; - } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) { + } else if ((cas_5_0_available == true) && + (sdram_freq <= cycle_5_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK; *selected_cas = DDR_CAS_5; } else { @@ -1677,7 +1675,7 @@ static void program_mode(unsigned long *dimm_populated, } } - if (sdram_ddr1 == TRUE) + if (sdram_ddr1 == true) mmode |= SDRAM_MMODE_WR_DDR1; else { @@ -1851,16 +1849,16 @@ static void program_tr(unsigned long *dimm_populated, t_wpc_ns = 0; t_wtr_ns = 0; t_rpc_ns = 0; - sdram_ddr1 = TRUE; + sdram_ddr1 = true; /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) { if (dimm_populated[dimm_num] == SDRAM_DDR2) - sdram_ddr1 = TRUE; + sdram_ddr1 = true; else - sdram_ddr1 = FALSE; + sdram_ddr1 = false; t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); @@ -1925,7 +1923,7 @@ static void program_tr(unsigned long *dimm_populated, break; } - if (sdram_ddr1 == TRUE) { /* DDR1 */ + if (sdram_ddr1 == true) { /* DDR1 */ if (sdram_freq < 200000000) { sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; @@ -2548,8 +2546,8 @@ calibration_loop: current_pass_length = 0; current_fail_length = 0; current_start = 0; - fail_found = FALSE; - pass_found = FALSE; + fail_found = false; + pass_found = false; /* * get the delay line calibration register value @@ -2570,8 +2568,8 @@ calibration_loop: * See if the rffd value passed. *-----------------------------------------------------------------*/ if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) current_start = rffd; @@ -2589,11 +2587,10 @@ calibration_loop: current_fail_length++; if (current_fail_length >= (dly_val >> 2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { + if (fail_found == false) + fail_found = true; + else if (pass_found == true) break; - } } } } /* for rffd */ @@ -2618,9 +2615,9 @@ calibration_loop: current_pass_length = 0; current_fail_length = 0; current_start = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; + window_found = false; + fail_found = false; + pass_found = false; for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { mfsdram(SDRAM_RQDC, rqdc_reg); @@ -2635,8 +2632,8 @@ calibration_loop: * See if the rffd value passed. *-----------------------------------------------------------------*/ if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) current_start = rqfd; @@ -2653,10 +2650,10 @@ calibration_loop: current_pass_length = 0; current_fail_length++; - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; + if (fail_found == false) { + fail_found = true; + } else if (pass_found == true) { + window_found = true; break; } } @@ -2667,7 +2664,7 @@ calibration_loop: /*------------------------------------------------------------------ * Make sure we found the valid read passing window. Halt if not *-----------------------------------------------------------------*/ - if (window_found == FALSE) { + if (window_found == false) { if (rqfd_start < SDRAM_RQDC_RQFD_MAX) { putc('\b'); putc(slash[loopi++ % 8]); @@ -2769,13 +2766,13 @@ static void test(void) mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_NON); - window_found = FALSE; - begin_found[0] = FALSE; - end_found[0] = FALSE; - search_end[0] = FALSE; - begin_found[1] = FALSE; - end_found[1] = FALSE; - search_end[1] = FALSE; + window_found = false; + begin_found[0] = false; + end_found[0] = false; + search_end[0] = false; + begin_found[1] = false; + end_found[1] = false; + search_end[1] = false; for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]); @@ -2812,32 +2809,32 @@ static void test(void) * See if the rffd value passed. *-----------------------------------------------------------------*/ if (i < NUMMEMTESTS) { - if ((end_found[dimm_num] == FALSE) && - (search_end[dimm_num] == TRUE)) { - end_found[dimm_num] = TRUE; + if ((end_found[dimm_num] == false) && + (search_end[dimm_num] == true)) { + end_found[dimm_num] = true; } - if ((end_found[0] == TRUE) && - (end_found[1] == TRUE)) + if ((end_found[0] == true) && + (end_found[1] == true)) break; } else { - if (begin_found[dimm_num] == FALSE) { - begin_found[dimm_num] = TRUE; - search_end[dimm_num] = TRUE; + if (begin_found[dimm_num] == false) { + begin_found[dimm_num] = true; + search_end[dimm_num] = true; } } } else { - begin_found[dimm_num] = TRUE; - end_found[dimm_num] = TRUE; + begin_found[dimm_num] = true; + end_found[dimm_num] = true; } } - if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE)) - window_found = TRUE; + if ((begin_found[0] == true) && (begin_found[1] == true)) + window_found = true; /*------------------------------------------------------------------ * Make sure we found the valid read passing window. Halt if not *-----------------------------------------------------------------*/ - if (window_found == FALSE) { + if (window_found == false) { printf("ERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); spd_ddr_init_hang (); diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index ce769a7..3ceab32 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -53,13 +53,6 @@ /*-----------------------------------------------------------------------------+ * Defines *-----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #define MAXDIMMS 2 #define MAXRANKS 2 @@ -279,7 +272,7 @@ static void get_spd_info(unsigned long dimm_ranks[], unsigned long num_dimm_banks) { unsigned long dimm_num; - unsigned long dimm_found = FALSE; + unsigned long dimm_found = false; unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1; unsigned char num_of_bytes; unsigned char total_size; @@ -334,7 +327,7 @@ static void get_spd_info(unsigned long dimm_ranks[], "\n\n"); spd_ddr_init_hang(); } - dimm_found = TRUE; + dimm_found = true; debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM" "\n", dimm_num, ranks_on_dimm); if (ranks_on_dimm > max_ranks_per_dimm) { @@ -355,7 +348,7 @@ static void get_spd_info(unsigned long dimm_ranks[], debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR: No memory installed.\n"); printf("Install at least one DDR2 DIMM.\n\n"); spd_ddr_init_hang(); @@ -882,7 +875,7 @@ static void program_ddr0_22(unsigned long dimm_ranks[], /* Check for ECC */ if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) & 0x02)) { - ecc_available = FALSE; + ecc_available = false; } } } |