diff options
| author | York Sun <york.sun@nxp.com> | 2016-11-18 19:30:56 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-24 07:42:11 (GMT) |
| commit | cefe11cdb2a0d1fe0daf90408d3c49e627ef39a7 (patch) | |
| tree | 028af2626c6f923a7630e1875fcfebfc1e5e06ee /arch/powerpc | |
| parent | 529fb062081e100faae6dc0d163a548b8528ff24 (diff) | |
| download | u-boot-fsl-qoriq-cefe11cdb2a0d1fe0daf90408d3c49e627ef39a7.tar.xz | |
powerpc: P5020: Remove macro CONFIG_PPC_P5020
Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_secure_boot.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 2 |
5 files changed, 9 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index a68a651..808144e 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -51,6 +51,7 @@ config TARGET_P4080DS config TARGET_P5020DS bool "Support P5020DS" select PHYS_64BIT + select ARCH_P5020 config TARGET_P5040DS bool "Support P5040DS" @@ -324,6 +325,9 @@ config ARCH_P3041 config ARCH_P4080 bool +config ARCH_P5020 + bool + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 0ea5547..edd365a 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -42,7 +42,7 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o obj-$(CONFIG_ARCH_P2041) += p2041_ids.o obj-$(CONFIG_ARCH_P3041) += p3041_ids.o obj-$(CONFIG_ARCH_P4080) += p4080_ids.o -obj-$(CONFIG_PPC_P5020) += p5020_ids.o +obj-$(CONFIG_ARCH_P5020) += p5020_ids.o obj-$(CONFIG_PPC_P5040) += p5040_ids.o obj-$(CONFIG_PPC_T4240) += t4240_ids.o obj-$(CONFIG_PPC_T4160) += t4240_ids.o @@ -84,7 +84,7 @@ obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o -obj-$(CONFIG_PPC_P5020) += p5020_serdes.o +obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o obj-$(CONFIG_PPC_P5040) += p5040_serdes.o obj-$(CONFIG_PPC_T4240) += t4240_serdes.o obj-$(CONFIG_PPC_T4160) += t4240_serdes.o diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 011aec6..496b845 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -429,7 +429,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 -#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ +#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 38b666c..47c3d98 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -60,7 +60,7 @@ #if defined(CONFIG_ARCH_P3041) || \ defined(CONFIG_ARCH_P4080) || \ - defined(CONFIG_PPC_P5020) || \ + defined(CONFIG_ARCH_P5020) || \ defined(CONFIG_PPC_P5040) || \ defined(CONFIG_ARCH_P2041) #define CONFIG_FSL_TRUST_ARCH_v1 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 83f8b8f..759671a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1857,7 +1857,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif #if defined(CONFIG_ARCH_P2041) || \ - defined(CONFIG_ARCH_P3041) || defined(CONFIG_PPC_P5020) + defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 |