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| author | Zang Roy-R61911 <tie-fei.zang@freescale.com> | 2013-11-28 05:23:37 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-12-04 22:54:42 (GMT) |
| commit | e88f421e7a65e5bd0c6131e5202d710e73dd4aae (patch) | |
| tree | 29daad933328ec9d6d20b8861399ec8f68319e45 /arch/powerpc | |
| parent | 7aa6c455c357f6d767acec747bbecb23664eeacb (diff) | |
| download | u-boot-fsl-qoriq-e88f421e7a65e5bd0c6131e5202d710e73dd4aae.tar.xz | |
T4240: Address T4240/T4160 Rev2.0 DDR clock change
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 1a58a19..46ae80c 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -86,6 +86,14 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of + * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 + * it uses 6. + */ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) + if (SVR_MAJ(get_svr()) >= 2) + mem_pll_rat *= 2; +#endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; else |