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| author | Simon Glass <sjg@chromium.org> | 2014-11-13 05:42:09 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-11-21 06:34:11 (GMT) |
| commit | d1cd045982b1e1e4db2c1cc2b2b932f739b78a11 (patch) | |
| tree | 042be9d3ac848c6799756f5e7fc6c1a6391d1d2a /arch/x86/cpu/coreboot/coreboot.c | |
| parent | fce7b2768364366bd4c4af9188186f6b3f9c2fe8 (diff) | |
| download | u-boot-fsl-qoriq-d1cd045982b1e1e4db2c1cc2b2b932f739b78a11.tar.xz | |
x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.
On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/coreboot/coreboot.c')
| -rw-r--r-- | arch/x86/cpu/coreboot/coreboot.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 8501716..0760a61 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -15,6 +15,7 @@ #include <asm/cache.h> #include <asm/cpu.h> #include <asm/io.h> +#include <asm/post.h> #include <asm/arch-coreboot/tables.h> #include <asm/arch-coreboot/sysinfo.h> #include <asm/arch/timestamp.h> @@ -70,7 +71,7 @@ void show_boot_progress(int val) gd->arch.tsc_prev = now; } #endif - outb(val, 0x80); + outb(val, POST_PORT); } int print_cpuinfo(void) |