x86: Move Intel Management Engine code to a common place

Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

5 files changed, 3 insertions, 318 deletions

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 78006f1..9cdb07b 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -11,10 +11,8 @@ obj-y += cpu.o
 obj-y += early_me.o
 obj-y += gma.o
 obj-y += lpc.o
-obj-y += me_status.o
 obj-y += model_206ax.o
 obj-y += northbridge.o
-obj-y += report_platform.o
 obj-y += sata.o
 obj-y += sdram.o
 endif
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index b1df77d..cda96ab 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -27,35 +27,6 @@ static const char *const me_ack_values[] = {
 	[ME_HFS_ACK_CONTINUE]	= "Continue to boot"
 };
 
-static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
-				      int offset)
-{
-	u32 dword;
-
-	dm_pci_read_config32(me_dev, offset, &dword);
-	memcpy(ptr, &dword, sizeof(dword));
-}
-
-static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
-				       int offset)
-{
-	u32 dword = 0;
-
-	memcpy(&dword, ptr, sizeof(dword));
-	dm_pci_write_config32(me_dev, offset, dword);
-}
-
-void intel_early_me_status(struct udevice *me_dev)
-{
-	struct me_hfs hfs;
-	struct me_gmes gmes;
-
-	pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
-	pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
-
-	intel_me_status(&hfs, &gmes);
-}
-
 int intel_early_me_init(struct udevice *me_dev)
 {
 	int count;
@@ -159,7 +130,7 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
 	debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
 
 	/* Check status after acknowledgement */
-	intel_early_me_status(me_dev);
+	intel_me_status(me_dev);
 
 	switch (hfs.ack_data) {
 	case ME_HFS_ACK_CONTINUE:
diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/ivybridge/me_status.c
deleted file mode 100644
index 15cf69f..0000000
--- a/arch/x86/cpu/ivybridge/me_status.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * From Coreboot src/southbridge/intel/bd82x6x/me_status.c
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#include <common.h>
-#include <asm/arch/me.h>
-
-/* HFS1[3:0] Current Working State Values */
-static const char *const me_cws_values[] = {
-	[ME_HFS_CWS_RESET]	= "Reset",
-	[ME_HFS_CWS_INIT]	= "Initializing",
-	[ME_HFS_CWS_REC]	= "Recovery",
-	[ME_HFS_CWS_NORMAL]	= "Normal",
-	[ME_HFS_CWS_WAIT]	= "Platform Disable Wait",
-	[ME_HFS_CWS_TRANS]	= "OP State Transition",
-	[ME_HFS_CWS_INVALID]	= "Invalid CPU Plugged In"
-};
-
-/* HFS1[8:6] Current Operation State Values */
-static const char *const me_opstate_values[] = {
-	[ME_HFS_STATE_PREBOOT]	= "Preboot",
-	[ME_HFS_STATE_M0_UMA]	= "M0 with UMA",
-	[ME_HFS_STATE_M3]	= "M3 without UMA",
-	[ME_HFS_STATE_M0]	= "M0 without UMA",
-	[ME_HFS_STATE_BRINGUP]	= "Bring up",
-	[ME_HFS_STATE_ERROR]	= "M0 without UMA but with error"
-};
-
-/* HFS[19:16] Current Operation Mode Values */
-static const char *const me_opmode_values[] = {
-	[ME_HFS_MODE_NORMAL]	= "Normal",
-	[ME_HFS_MODE_DEBUG]	= "Debug",
-	[ME_HFS_MODE_DIS]	= "Soft Temporary Disable",
-	[ME_HFS_MODE_OVER_JMPR]	= "Security Override via Jumper",
-	[ME_HFS_MODE_OVER_MEI]	= "Security Override via MEI Message"
-};
-
-/* HFS[15:12] Error Code Values */
-static const char *const me_error_values[] = {
-	[ME_HFS_ERROR_NONE]	= "No Error",
-	[ME_HFS_ERROR_UNCAT]	= "Uncategorized Failure",
-	[ME_HFS_ERROR_IMAGE]	= "Image Failure",
-	[ME_HFS_ERROR_DEBUG]	= "Debug Failure"
-};
-
-/* GMES[31:28] ME Progress Code */
-static const char *const me_progress_values[] = {
-	[ME_GMES_PHASE_ROM]	= "ROM Phase",
-	[ME_GMES_PHASE_BUP]	= "BUP Phase",
-	[ME_GMES_PHASE_UKERNEL]	= "uKernel Phase",
-	[ME_GMES_PHASE_POLICY]	= "Policy Module",
-	[ME_GMES_PHASE_MODULE]	= "Module Loading",
-	[ME_GMES_PHASE_UNKNOWN]	= "Unknown",
-	[ME_GMES_PHASE_HOST]	= "Host Communication"
-};
-
-/* GMES[27:24] Power Management Event */
-static const char *const me_pmevent_values[] = {
-	[0x00] = "Clean Moff->Mx wake",
-	[0x01] = "Moff->Mx wake after an error",
-	[0x02] = "Clean global reset",
-	[0x03] = "Global reset after an error",
-	[0x04] = "Clean Intel ME reset",
-	[0x05] = "Intel ME reset due to exception",
-	[0x06] = "Pseudo-global reset",
-	[0x07] = "S0/M0->Sx/M3",
-	[0x08] = "Sx/M3->S0/M0",
-	[0x09] = "Non-power cycle reset",
-	[0x0a] = "Power cycle reset through M3",
-	[0x0b] = "Power cycle reset through Moff",
-	[0x0c] = "Sx/Mx->Sx/Moff"
-};
-
-/* Progress Code 0 states */
-static const char *const me_progress_rom_values[] = {
-	[0x00] = "BEGIN",
-	[0x06] = "DISABLE"
-};
-
-/* Progress Code 1 states */
-static const char *const me_progress_bup_values[] = {
-	[0x00] = "Initialization starts",
-	[0x01] = "Disable the host wake event",
-	[0x04] = "Flow determination start process",
-	[0x08] = "Error reading/matching the VSCC table in the descriptor",
-	[0x0a] = "Check to see if straps say ME DISABLED",
-	[0x0b] = "Timeout waiting for PWROK",
-	[0x0d] = "Possibly handle BUP manufacturing override strap",
-	[0x11] = "Bringup in M3",
-	[0x12] = "Bringup in M0",
-	[0x13] = "Flow detection error",
-	[0x15] = "M3 clock switching error",
-	[0x18] = "M3 kernel load",
-	[0x1c] = "T34 missing - cannot program ICC",
-	[0x1f] = "Waiting for DID BIOS message",
-	[0x20] = "Waiting for DID BIOS message failure",
-	[0x21] = "DID reported an error",
-	[0x22] = "Enabling UMA",
-	[0x23] = "Enabling UMA error",
-	[0x24] = "Sending DID Ack to BIOS",
-	[0x25] = "Sending DID Ack to BIOS error",
-	[0x26] = "Switching clocks in M0",
-	[0x27] = "Switching clocks in M0 error",
-	[0x28] = "ME in temp disable",
-	[0x32] = "M0 kernel load",
-};
-
-/* Progress Code 3 states */
-static const char *const me_progress_policy_values[] = {
-	[0x00] = "Entery into Policy Module",
-	[0x03] = "Received S3 entry",
-	[0x04] = "Received S4 entry",
-	[0x05] = "Received S5 entry",
-	[0x06] = "Received UPD entry",
-	[0x07] = "Received PCR entry",
-	[0x08] = "Received NPCR entry",
-	[0x09] = "Received host wake",
-	[0x0a] = "Received AC<>DC switch",
-	[0x0b] = "Received DRAM Init Done",
-	[0x0c] = "VSCC Data not found for flash device",
-	[0x0d] = "VSCC Table is not valid",
-	[0x0e] = "Flash Partition Boundary is outside address space",
-	[0x0f] = "ME cannot access the chipset descriptor region",
-	[0x10] = "Required VSCC values for flash parts do not match",
-};
-
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
-{
-	/* Check Current States */
-	debug("ME: FW Partition Table      : %s\n",
-	      hfs->fpt_bad ? "BAD" : "OK");
-	debug("ME: Bringup Loader Failure  : %s\n",
-	      hfs->ft_bup_ld_flr ? "YES" : "NO");
-	debug("ME: Firmware Init Complete  : %s\n",
-	      hfs->fw_init_complete ? "YES" : "NO");
-	debug("ME: Manufacturing Mode      : %s\n",
-	      hfs->mfg_mode ? "YES" : "NO");
-	debug("ME: Boot Options Present    : %s\n",
-	      hfs->boot_options_present ? "YES" : "NO");
-	debug("ME: Update In Progress      : %s\n",
-	      hfs->update_in_progress ? "YES" : "NO");
-	debug("ME: Current Working State   : %s\n",
-	      me_cws_values[hfs->working_state]);
-	debug("ME: Current Operation State : %s\n",
-	      me_opstate_values[hfs->operation_state]);
-	debug("ME: Current Operation Mode  : %s\n",
-	      me_opmode_values[hfs->operation_mode]);
-	debug("ME: Error Code              : %s\n",
-	      me_error_values[hfs->error_code]);
-	debug("ME: Progress Phase          : %s\n",
-	      me_progress_values[gmes->progress_code]);
-	debug("ME: Power Management Event  : %s\n",
-	      me_pmevent_values[gmes->current_pmevent]);
-
-	debug("ME: Progress Phase State    : ");
-	switch (gmes->progress_code) {
-	case ME_GMES_PHASE_ROM:		/* ROM Phase */
-		debug("%s", me_progress_rom_values[gmes->current_state]);
-		break;
-
-	case ME_GMES_PHASE_BUP:		/* Bringup Phase */
-		if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) &&
-		    me_progress_bup_values[gmes->current_state])
-			debug("%s",
-			      me_progress_bup_values[gmes->current_state]);
-		else
-			debug("0x%02x", gmes->current_state);
-		break;
-
-	case ME_GMES_PHASE_POLICY:	/* Policy Module Phase */
-		if (gmes->current_state <
-				ARRAY_SIZE(me_progress_policy_values) &&
-		    me_progress_policy_values[gmes->current_state])
-			debug("%s",
-			      me_progress_policy_values[gmes->current_state]);
-		else
-			debug("0x%02x", gmes->current_state);
-		break;
-
-	case ME_GMES_PHASE_HOST:	/* Host Communication Phase */
-		if (!gmes->current_state)
-			debug("Host communication established");
-		else
-			debug("0x%02x", gmes->current_state);
-		break;
-
-	default:
-		debug("Unknown 0x%02x", gmes->current_state);
-	}
-	debug("\n");
-}
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c
deleted file mode 100644
index c78322a..0000000
--- a/arch/x86/cpu/ivybridge/report_platform.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * From Coreboot src/northbridge/intel/sandybridge/report_platform.c
- *
- * Copyright (C) 2012 Google Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#include <common.h>
-#include <asm/cpu.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-#include <asm/arch/sandybridge.h>
-
-static void report_cpu_info(void)
-{
-	char cpu_string[CPU_MAX_NAME_LEN], *cpu_name;
-	const char *mode[] = {"NOT ", ""};
-	struct cpuid_result cpuidr;
-	int vt, txt, aes;
-	u32 index;
-
-	index = 0x80000000;
-	cpuidr = cpuid(index);
-	if (cpuidr.eax < 0x80000004) {
-		strcpy(cpu_string, "Platform info not available");
-		cpu_name = cpu_string;
-	} else {
-		cpu_name = cpu_get_name(cpu_string);
-	}
-
-	cpuidr = cpuid(1);
-	debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name);
-	aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
-	txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
-	vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
-	debug("AES %ssupported, TXT %ssupported, VT %ssupported\n",
-	      mode[aes], mode[txt], mode[vt]);
-}
-
-/* The PCI id name match comes from Intel document 472178 */
-static struct {
-	u16 dev_id;
-	const char *dev_name;
-} pch_table[] = {
-	{0x1E41, "Desktop Sample"},
-	{0x1E42, "Mobile Sample"},
-	{0x1E43, "SFF Sample"},
-	{0x1E44, "Z77"},
-	{0x1E45, "H71"},
-	{0x1E46, "Z75"},
-	{0x1E47, "Q77"},
-	{0x1E48, "Q75"},
-	{0x1E49, "B75"},
-	{0x1E4A, "H77"},
-	{0x1E53, "C216"},
-	{0x1E55, "QM77"},
-	{0x1E56, "QS77"},
-	{0x1E58, "UM77"},
-	{0x1E57, "HM77"},
-	{0x1E59, "HM76"},
-	{0x1E5D, "HM75"},
-	{0x1E5E, "HM70"},
-	{0x1E5F, "NM70"},
-};
-
-static void report_pch_info(struct udevice *dev)
-{
-	const char *pch_type = "Unknown";
-	int i;
-	u16 dev_id;
-	uint8_t rev_id;
-
-	dm_pci_read_config16(dev, 2, &dev_id);
-	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
-		if (pch_table[i].dev_id == dev_id) {
-			pch_type = pch_table[i].dev_name;
-			break;
-		}
-	}
-	dm_pci_read_config8(dev, 8, &rev_id);
-	debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
-	      rev_id);
-}
-
-void report_platform_info(struct udevice *dev)
-{
-	report_cpu_info();
-	report_pch_info(dev);
-}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index f7dd61f..e0296a2 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -27,6 +27,7 @@
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
+#include <asm/report_platform.h>
 #include <asm/arch/me.h>
 #include <asm/arch/pei_data.h>
 #include <asm/arch/pch.h>
@@ -384,7 +385,7 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
 	if (BASE_REV_SNB == done)
 		intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
 	else
-		intel_early_me_status(me_dev);
+		intel_me_status(me_dev);
 
 	post_system_agent_init(pei_data);
 	report_memory_config();