diff options
| author | Simon Glass <sjg@chromium.org> | 2016-03-12 05:06:56 (GMT) |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 02:27:24 (GMT) |
| commit | bb096b9fad65696798ffd1637b30d9cc7951e70c (patch) | |
| tree | 1f9ba8d5ee21a6a0097e83db70ca980e1cfaced1 /arch/x86/cpu/ivybridge | |
| parent | 06d336cca284cc767a095ce40afca79b4aa0ecb0 (diff) | |
| download | u-boot-fsl-qoriq-bb096b9fad65696798ffd1637b30d9cc7951e70c.tar.xz | |
x86: Add the root-complex block to common intel registers
This is similar to MCH in that it is used in various drivers. Add it to
the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/ivybridge')
| -rw-r--r-- | arch/x86/cpu/ivybridge/bd82x6x.c | 1 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/lpc.c | 6 |
2 files changed, 5 insertions, 2 deletions
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 9972b0a..55057e0 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -11,6 +11,7 @@ #include <pch.h> #include <syscon.h> #include <asm/cpu.h> +#include <asm/intel_regs.h> #include <asm/io.h> #include <asm/lapic.h> #include <asm/pci.h> diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 9ab5ed3..26ffaa0 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -13,6 +13,7 @@ #include <rtc.h> #include <pci.h> #include <asm/acpi.h> +#include <asm/intel_regs.h> #include <asm/interrupt.h> #include <asm/io.h> #include <asm/ioapic.h> @@ -420,7 +421,7 @@ static void enable_spi_prefetch(struct udevice *pch) static void enable_port80_on_lpc(struct udevice *pch) { /* Enable port 80 POST on LPC */ - dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); clrbits_le32(RCB_REG(GCS), 4); } @@ -552,7 +553,8 @@ static int bd82x6x_lpc_early_init(struct udevice *dev) { /* Setting up Southbridge. In the northbridge code. */ debug("Setting up static southbridge registers\n"); - dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, + RCB_BASE_ADDRESS | 1); dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ |