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| author | Simon Glass <sjg@chromium.org> | 2015-07-04 00:28:27 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-07-15 00:03:19 (GMT) |
| commit | b9da5086b88a1565c7aede14e68bef2456c44475 (patch) | |
| tree | f4817c1fc0bfa495fc69a15089da614e84af561f /arch/x86 | |
| parent | b71f9dca89013b8b100006029c98d04b495ebdf7 (diff) | |
| download | u-boot-fsl-qoriq-b9da5086b88a1565c7aede14e68bef2456c44475.tar.xz | |
dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 9afdafb..af927b9 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -353,6 +353,8 @@ int x86_cpu_init_f(void) gd->arch.has_mtrr = has_mtrr(); } + /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ + gd->pci_ram_top = 0x80000000U; /* Configure fixed range MTRRs for some legacy regions */ if (gd->arch.has_mtrr) { |