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| author | Tom Rini <trini@konsulko.com> | 2015-11-30 12:10:49 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-11-30 12:10:49 (GMT) |
| commit | 30f56399e7c740be043ecbc57cd96ce95998208a (patch) | |
| tree | 062c5922499ae64a0c56967a37a4f1aa3f6d4904 /arch | |
| parent | a71d99ac03c8d5d9622962344485b04aade27b67 (diff) | |
| parent | 6623aee5b6aba2f8efe9b7d2417f090f9c2b3cd3 (diff) | |
| download | u-boot-fsl-qoriq-30f56399e7c740be043ecbc57cd96ce95998208a.tar.xz | |
Merge git://www.denx.de/git/u-boot-ppc4xx
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/Kconfig | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/start.S | 23 |
2 files changed, 1 insertions, 24 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 945e771..efd3165 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -152,7 +152,7 @@ source "board/gdsys/405ex/Kconfig" source "board/gdsys/dlvision/Kconfig" source "board/gdsys/gdppc440etx/Kconfig" source "board/gdsys/intip/Kconfig" -source "board/lwmon5/Kconfig" +source "board/liebherr/lwmon5/Kconfig" source "board/mosaixtech/icon/Kconfig" source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 77d4040..3dd0557 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1795,34 +1795,11 @@ ppc405ep_init: ..no_pllset: #endif /* CONFIG_BUBINGA */ -#ifdef CONFIG_TAIHU - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ - addis r5,0,CPLD_REG0_ADDR@h - ori r5,r5,CPLD_REG0_ADDR@l - andi. r5, r5, 0x10 - bne _pci_66mhz -#endif /* CONFIG_TAIHU */ - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ ori r3,r3,PLLMR0_DEFAULT@l /* */ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ ori r4,r4,PLLMR1_DEFAULT@l /* */ -#ifdef CONFIG_TAIHU - b 1f -_pci_66mhz: - addis r3,0,PLLMR0_DEFAULT_PCI66@h - ori r3,r3,PLLMR0_DEFAULT_PCI66@l - addis r4,0,PLLMR1_DEFAULT_PCI66@h - ori r4,r4,PLLMR1_DEFAULT_PCI66@l - b 1f -strap_1: - mfdcr r3, CPC0_PLLMR0 - mfdcr r4, CPC0_PLLMR1 -#endif /* CONFIG_TAIHU */ - 1: b pll_write /* Write the CPC0_PLLMR with new value */ |