diff options
author | Tom Rini <trini@konsulko.com> | 2017-04-13 21:31:06 (GMT) |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2017-04-13 21:31:06 (GMT) |
commit | b7b24a7a3cd74bb165d28a2959ed9143e3648fbf (patch) | |
tree | 062fd13092cee10dc8746a1339ecea18f08d21d6 /arch | |
parent | 1622559066d890f1b7622be0ede8a5d64de66ef3 (diff) | |
parent | 22e10be456014400788f80d45fc5f5c0b9d4a81d (diff) | |
download | u-boot-fsl-qoriq-b7b24a7a3cd74bb165d28a2959ed9143e3648fbf.tar.xz |
Merge git://git.denx.de/u-boot-dm
Here with some DM changes as well as the long-standing AT91 DM/DT
conversion patches which I have picked up via dm.
Diffstat (limited to 'arch')
40 files changed, 6543 insertions, 223 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aeb6674..68d2791 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -349,6 +349,23 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb +dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ + sama5d31ek.dtb \ + sama5d33ek.dtb \ + sama5d34ek.dtb \ + sama5d35ek.dtb \ + sama5d36ek.dtb \ + sama5d36ek_cmp.dtb + +dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ + at91-sama5d3_xplained.dtb + +dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ + at91-sama5d4ek.dtb + +dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ + at91-sama5d4_xplained.dtb + dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-a.dtb \ diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts b/arch/arm/dts/at91-sama5d3_xplained.dts new file mode 100644 index 0000000..6959710 --- /dev/null +++ b/arch/arm/dts/at91-sama5d3_xplained.dts @@ -0,0 +1,348 @@ +/* + * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "SAMA5D3 Xplained"; + compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &dbgu; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + mmc0: mmc@f0000000 { + u-boot,dm-pre-reloc; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + }; + }; + + mmc1: mmc@f8000000 { + u-boot,dm-pre-reloc; + vmmc-supply = <&vcc_3v3_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "disabled"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>; + }; + }; + + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "disabled"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG1 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + vddana_reg: LDO_REG2 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + }; + + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + }; + }; + + pwm0: pwm@f002c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>; + status = "okay"; + }; + + usart0: serial@f001c000 { + status = "okay"; + }; + + usart1: serial@f0020000 { + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + uart0: serial@f0024000 { + status = "okay"; + }; + + mmc1: mmc@f8000000 { + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>; + }; + }; + + spi1: spi@f8008000 { + cs-gpios = <&pioC 25 0>; + status = "okay"; + }; + + adc0: adc@f8018000 { + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7 + &pinctrl_adc0_ad8 + &pinctrl_adc0_ad9 + >; + status = "okay"; + }; + + i2c2: i2c@f801c000 { + dmas = <0>, <0>; /* Do not use DMA for i2c2 */ + pinctrl-0 = <&pinctrl_i2c2_pu>; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + dbgu: serial@ffffee00 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + pinctrl@fffff200 { + board { + u-boot,dm-pre-reloc; + pinctrl_i2c0_pu: i2c0_pu { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_i2c2_pu: i2c2_pu { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>, + <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + pinctrl_mmc0_cd: mmc0_cd { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + pinctrl_mmc1_cd: mmc1_cd { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */ + }; + }; + }; + }; + + nand0: nand@60000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + + usb0: gadget@00500000 { + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00600000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 3 GPIO_ACTIVE_LOW + &pioE 4 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@00700000 { + status = "okay"; + }; + }; + + vcc_mmc0_reg: fixedregulator@0 { + compatible = "regulator-fixed"; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + bp3 { + label = "PB_USER"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + d2 { + label = "d2"; + gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ + linux,default-trigger = "heartbeat"; + }; + + d3 { + label = "d3"; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm/dts/at91-sama5d4_xplained.dts b/arch/arm/dts/at91-sama5d4_xplained.dts new file mode 100644 index 0000000..ca6aff2 --- /dev/null +++ b/arch/arm/dts/at91-sama5d4_xplained.dts @@ -0,0 +1,286 @@ +/* + * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board + * + * Copyright (C) 2015 Atmel, + * 2015 Josh Wu <josh.wu@atmel.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "Atmel SAMA5D4 Xplained"; + compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &usart3; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f8010000 { + u-boot,dm-pre-reloc; + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + spi_flash@0 { + u-boot,dm-pre-reloc; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + }; + + macb0: ethernet@f8020000 { + phy-mode = "rmii"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + + phy0: ethernet-phy@1 { + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + }; + }; + + mmc1: mmc@fc000000 { + u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + vmmc-supply = <&vcc_mmc1_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 3 0>; + }; + }; + + usart3: serial@fc00c000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + spi1: spi@fc018000 { + cs-gpios = <&pioB 21 0>; + status = "okay"; + }; + + adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + atmel,adc-vref = <3300>; + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + u-boot,dm-pre-reloc; + pinctrl_mmc1_cd: mmc1_cd { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + <AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_macb0_phy_irq: macb0_phy_irq_0 { + atmel,pins = + <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + }; + }; + }; + + usb0: gadget@00400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioE 11 GPIO_ACTIVE_HIGH + &pioE 14 GPIO_ACTIVE_HIGH + >; + status = "okay"; + }; + + usb2: ehci@00600000 { + status = "okay"; + }; + + nand0: nand@80000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + atmel,has-pmecc; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + d8 { + label = "d8"; + gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + d10 { + label = "d10"; + gpios = <&pioE 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_3v3_reg: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VCC 3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + reg = <0 1>; + }; + + vcc_mmc1_reg: fixedregulator@1 { + compatible = "regulator-fixed"; + gpio = <&pioE 4 GPIO_ACTIVE_LOW>; + regulator-name = "VDD MCI1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_reg>; + regulator-always-on; + reg = <1 1>; + }; +}; diff --git a/arch/arm/dts/at91-sama5d4ek.dts b/arch/arm/dts/at91-sama5d4ek.dts new file mode 100644 index 0000000..b965f5b --- /dev/null +++ b/arch/arm/dts/at91-sama5d4ek.dts @@ -0,0 +1,341 @@ +/* + * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "Atmel SAMA5D4-EK"; + compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &usart3; + }; + + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + adc0: adc@fc034000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger conflicts with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ + atmel,adc-vref = <3300>; + /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ + status = "okay"; /* Enable ADC IIO support */ + }; + + mmc0: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 5 0>; + }; + }; + + ssc0: ssc@f8008000 { + status = "okay"; + }; + + spi0: spi@f8010000 { + u-boot,dm-pre-reloc; + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + spi_flash@0 { + u-boot,dm-pre-reloc; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck2>; + clock-names = "mclk"; + }; + + qt1070:keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioE>; + interrupts = <25 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + + atmel_mxt_ts@4c { + compatible = "atmel,atmel_mxt_ts"; + reg = <0x4c>; + interrupt-parent = <&pioE>; + interrupts = <24 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mxt_ts>; + }; + }; + + macb0: ethernet@f8020000 { + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioE>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + mmc1: mmc@fc000000 { + u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 6 0>; + }; + }; + + usart2: serial@fc008000 { + status = "okay"; + }; + + usart3: serial@fc00c000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + u-boot,dm-pre-reloc; + pinctrl_macb0_phy_irq: macb0_phy_irq { + atmel,pins = + <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_mmc1_cd: mmc1_cd { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_pck2_as_audio_mck: pck2_as_audio_mck { + atmel,pins = + <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + <AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */ + }; + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + <AT91_PIOE 25 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_mxt_ts: mxt_irq { + atmel,pins = + <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + }; + }; + }; + + usb0: gadget@00400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ + &pioE 11 GPIO_ACTIVE_LOW + &pioE 12 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@00600000 { + status = "okay"; + }; + + nand0: nand@80000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + atmel,has-pmecc; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + d8 { + label = "d8"; + /* PE28, conflicts with usart4 rts pin */ + gpios = <&pioE 28 GPIO_ACTIVE_LOW>; + }; + + d9 { + label = "d9"; + gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; + }; + + d10 { + label = "d10"; + gpios = <&pioE 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck2_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D4EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; +}; diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi new file mode 100644 index 0000000..84ee089 --- /dev/null +++ b/arch/arm/dts/sama5d3.dtsi @@ -0,0 +1,1539 @@ +/* + * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC + * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * Licensed under GPLv2 or later. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/at91.h> + +/ { + model = "Atmel SAMA5D3 family SoC"; + compatible = "atmel,sama5d3", "atmel,sama5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + serial5 = &uart0; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + ssc0 = &ssc0; + ssc1 = &ssc1; + pwm0 = &pwm0; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0x0>; + }; + }; + + pmu { + compatible = "arm,cortex-a5-pmu"; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + sram: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x20000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + mmc0: mmc@f0000000 { + compatible = "atmel,hsmci"; + reg = <0xf0000000 0x600>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + }; + + spi0: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf0004000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ssc0: ssc@f0008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0008000 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + tcb0: timer@f0010000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf0010000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + i2c0: i2c@f0014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf0014000 0x4000>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@f0018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf0018000 0x4000>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + + usart0: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f0020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0020000 0x100>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x100>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + pwm0: pwm@f002c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf002c000 0x300>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + status = "disabled"; + }; + + isi: isi@f0034000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0034000 0x4000>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + sfr: sfr@f0038000 { + compatible = "atmel,sama5d3-sfr", "syscon"; + reg = <0xf0038000 0x60>; + }; + + mmc1: mmc@f8000000 { + compatible = "atmel,hsmci"; + reg = <0xf8000000 0x600>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; + }; + + spi1: spi@f8008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8008000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + ssc1: ssc@f800c000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf800c000 0x4000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + adc0: adc@f8018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9x5-adc"; + reg = <0xf8018000 0x100>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7 + &pinctrl_adc0_ad8 + &pinctrl_adc0_ad9 + &pinctrl_adc0_ad10 + &pinctrl_adc0_ad11 + >; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0xfff>; + atmel,adc-startup-time = <40>; + atmel,adc-use-external-triggers; + atmel,adc-vref = <3000>; + atmel,adc-res = <10 12>; + atmel,adc-sample-hold-time = <11>; + atmel,adc-res-names = "lowres", "highres"; + status = "disabled"; + + trigger@0 { + reg = <0>; + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + }; + trigger@1 { + reg = <1>; + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + }; + trigger@2 { + reg = <2>; + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + }; + trigger@3 { + reg = <3>; + trigger-name = "continuous"; + trigger-value = <0x6>; + }; + }; + + i2c2: i2c@f801c000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf801c000 0x4000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi2_clk>; + status = "disabled"; + }; + + usart2: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x100>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + sha@f8034000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xf8034000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; + dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; + }; + + aes@f8038000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xf8038000 0x100>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; + dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; + }; + + tdes@f803c000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xf803c000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; + dma-names = "tx", "rx"; + clocks = <&tdes_clk>; + clock-names = "tdes_clk"; + }; + + trng@f8040000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xf8040000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&trng_clk>; + }; + + dma0: dma-controller@ffffe600 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffe600 0x200>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + dma1: dma-controller@ffffe800 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffe800 0x200>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <2>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xffffea00 0x200>; + clocks = <&ddrck>, <&mpddr_clk>; + clock-names = "ddrck", "mpddr"; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&dbgu_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d3-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <47>; + }; + + pinctrl@fffff200 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; + ranges = <0xfffff200 0xfffff200 0xa00>; + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ + 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ + 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ + 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ + 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ + >; + reg = <0xfffff200 0x100 /* pioA */ + 0xfffff400 0x100 /* pioB */ + 0xfffff600 0x100 /* pioC */ + 0xfffff800 0x100 /* pioD */ + 0xfffffa00 0x100 /* pioE */ + >; + + /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = + <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = + <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = + <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = + <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = + <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = + <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ + }; + pinctrl_adc0_ad5: adc0_ad5 { + atmel,pins = + <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ + }; + pinctrl_adc0_ad6: adc0_ad6 { + atmel,pins = + <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ + }; + pinctrl_adc0_ad7: adc0_ad7 { + atmel,pins = + <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ + }; + pinctrl_adc0_ad8: adc0_ad8 { + atmel,pins = + <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ + }; + pinctrl_adc0_ad9: adc0_ad9 { + atmel,pins = + <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ + }; + pinctrl_adc0_ad10: adc0_ad10 { + atmel,pins = + <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ + }; + pinctrl_adc0_ad11: adc0_ad11 { + atmel,pins = + <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ + }; + }; + + dbgu { + u-boot,dm-pre-reloc; + pinctrl_dbgu: dbgu-0 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ + AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ + AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ + AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ + }; + }; + + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ + AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ + AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ + AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ + AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ + AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ + AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ + AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ + AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ + AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ + AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ + }; + + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ + AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ + }; + + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */ + AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */ + }; + }; + + mmc0 { + u-boot,dm-pre-reloc; + pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ + AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ + AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ + }; + pinctrl_mmc0_dat1_3: mmc0_dat1_3 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ + AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ + AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ + }; + pinctrl_mmc0_dat4_7: mmc0_dat4_7 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ + AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ + AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ + AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ + }; + }; + + mmc1 { + u-boot,dm-pre-reloc; + pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ + AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ + }; + pinctrl_mmc1_dat1_3: mmc1_dat1_3 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ + AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ + }; + }; + + nand0 { + pinctrl_nand0_ale_cle: nand0_ale_cle-0 { + atmel,pins = + <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ + AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ + }; + }; + + pwm0 { + pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 { + atmel,pins = + <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */ + }; + pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */ + }; + pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 { + atmel,pins = + <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */ + }; + pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 { + atmel,pins = + <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */ + }; + + pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 { + atmel,pins = + <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */ + }; + pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 { + atmel,pins = + <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */ + }; + pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 { + atmel,pins = + <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */ + }; + pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 { + atmel,pins = + <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */ + }; + pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 { + atmel,pins = + <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */ + }; + pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */ + }; + + pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */ + }; + pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 { + atmel,pins = + <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */ + }; + pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 { + atmel,pins = + <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */ + }; + pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 { + atmel,pins = + <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */ + }; + + pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 { + atmel,pins = + <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */ + }; + pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 { + atmel,pins = + <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */ + }; + pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 { + atmel,pins = + <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */ + }; + pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 { + atmel,pins = + <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */ + }; + }; + + spi0 { + u-boot,dm-pre-reloc; + pinctrl_spi0: spi0-0 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ + AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ + AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + u-boot,dm-pre-reloc; + pinctrl_spi1: spi1-0 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ + AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ + AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ + AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ + AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ + AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ + AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* conflicts with PWMFI2, ISI_D8 */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* conflicts with TWD0, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* conflicts with TWCK0, ISI_HSYNC */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ + AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ + }; + + pinctrl_usart0_rts_cts: usart0_rts_cts-0 { + atmel,pins = + <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ + AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ + AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ + }; + + pinctrl_usart1_rts_cts: usart1_rts_cts-0 { + atmel,pins = + <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ + AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ + AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ + }; + + pinctrl_usart2_rts_cts: usart2_rts_cts-0 { + atmel,pins = + <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ + AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ + AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ + }; + + pinctrl_usart3_rts_cts: usart3_rts_cts-0 { + atmel,pins = + <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ + AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ + }; + }; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + u-boot,dm-pre-reloc; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + u-boot,dm-pre-reloc; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + u-boot,dm-pre-reloc; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + u-boot,dm-pre-reloc; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + u-boot,dm-pre-reloc; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,sama5d3-pmc", "syscon"; + reg = <0xfffffc00 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + u-boot,dm-pre-reloc; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc &main_osc>; + }; + + plla: pllack@0 { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <8000000 50000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <0 166000000>; + atmel,clk-divisors = <1 2 4 3>; + u-boot,dm-pre-reloc; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: progck@0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: progck@1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: progck@2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck@2 { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + smdck: smdck@4 { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpck@6 { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck@7 { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck@8 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck@9 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck@10 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + u-boot,dm-pre-reloc; + + dbgu_clk: dbgu_clk@2 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <2>; + }; + + hsmc_clk: hsmc_clk@5 { + #clock-cells = <0>; + reg = <5>; + }; + + pioA_clk: pioA_clk@6 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <6>; + }; + + pioB_clk: pioB_clk@7 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <7>; + }; + + pioC_clk: pioC_clk@8 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <8>; + }; + + pioD_clk: pioD_clk@9 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <9>; + }; + + pioE_clk: pioE_clk@10 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <10>; + }; + + usart0_clk: usart0_clk@12 { + #clock-cells = <0>; + reg = <12>; + atmel,clk-output-range = <0 66000000>; + }; + + usart1_clk: usart1_clk@13 { + #clock-cells = <0>; + reg = <13>; + atmel,clk-output-range = <0 66000000>; + }; + + usart2_clk: usart2_clk@14 { + #clock-cells = <0>; + reg = <14>; + atmel,clk-output-range = <0 66000000>; + }; + + usart3_clk: usart3_clk@15 { + #clock-cells = <0>; + reg = <15>; + atmel,clk-output-range = <0 66000000>; + }; + + uart0_clk: uart0_clk@16 { + #clock-cells = <0>; + reg = <16>; + atmel,clk-output-range = <0 66000000>; + }; + + twi0_clk: twi0_clk@18 { + reg = <18>; + #clock-cells = <0>; + atmel,clk-output-range = <0 16625000>; + }; + + twi1_clk: twi1_clk@19 { + #clock-cells = <0>; + reg = <19>; + atmel,clk-output-range = <0 16625000>; + }; + + twi2_clk: twi2_clk@20 { + #clock-cells = <0>; + reg = <20>; + atmel,clk-output-range = <0 16625000>; + }; + + mci0_clk: mci0_clk@21 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <21>; + }; + + mci1_clk: mci1_clk@22 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <22>; + }; + + spi0_clk: spi0_clk@24 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <24>; + atmel,clk-output-range = <0 133000000>; + }; + + spi1_clk: spi1_clk@25 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <25>; + atmel,clk-output-range = <0 133000000>; + }; + + tcb0_clk: tcb0_clk@26 { + #clock-cells = <0>; + reg = <26>; + atmel,clk-output-range = <0 133000000>; + }; + + pwm_clk: pwm_clk@28 { + #clock-cells = <0>; + reg = <28>; + }; + + adc_clk: adc_clk@29 { + #clock-cells = <0>; + reg = <29>; + atmel,clk-output-range = <0 66000000>; + }; + + dma0_clk: dma0_clk@30 { + #clock-cells = <0>; + reg = <30>; + }; + + dma1_clk: dma1_clk@31 { + #clock-cells = <0>; + reg = <31>; + }; + + uhphs_clk: uhphs_clk@32 { + #clock-cells = <0>; + reg = <32>; + }; + + udphs_clk: udphs_clk@33 { + #clock-cells = <0>; + reg = <33>; + }; + + isi_clk: isi_clk@37 { + #clock-cells = <0>; + reg = <37>; + }; + + ssc0_clk: ssc0_clk@38 { + #clock-cells = <0>; + reg = <38>; + atmel,clk-output-range = <0 66000000>; + }; + + ssc1_clk: ssc1_clk@39 { + #clock-cells = <0>; + reg = <39>; + atmel,clk-output-range = <0 66000000>; + }; + + sha_clk: sha_clk@42 { + #clock-cells = <0>; + reg = <42>; + }; + + aes_clk: aes_clk@43 { + #clock-cells = <0>; + reg = <43>; + }; + + tdes_clk: tdes_clk@44 { + #clock-cells = <0>; + reg = <44>; + }; + + trng_clk: trng_clk@45 { + #clock-cells = <0>; + reg = <45>; + }; + + fuse_clk: fuse_clk@48 { + #clock-cells = <0>; + reg = <48>; + }; + + mpddr_clk: mpddr_clk@49 { + #clock-cells = <0>; + reg = <49>; + }; + }; + }; + + rstc@fffffe00 { + compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k>; + }; + + shutdown-controller@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&mck>; + }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + status = "disabled"; + }; + + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + rtc@fffffeb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffeb0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + }; + }; + + usb0: gadget@00500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,sama5d3-udc"; + reg = <0x00500000 0x100000 + 0xf8030000 0x4000>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep0: endpoint@0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1: endpoint@1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2: endpoint@2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3: endpoint@3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep4: endpoint@4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep5: endpoint@5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep6: endpoint@6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep7i: endpoint@7 { + reg = <7>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep8: endpoint@8 { + reg = <8>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep9: endpoint@9 { + reg = <9>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep10: endpoint@10 { + reg = <10>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep11: endpoint@11 { + reg = <11>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep12: endpoint@12 { + reg = <12>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep13: endpoint@13 { + reg = <13>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep14: endpoint@14 { + reg = <14>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep15: endpoint@15 { + reg = <15>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + }; + + usb1: ohci@00600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@00700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + nand0: nand@60000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = < 0x60000000 0x01000000 /* EBI CS3 */ + 0xffffc070 0x00000490 /* SMC PMECC regs */ + 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ + 0x00110000 0x00018000 /* ROM code */ + >; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand0_ale_cle>; + atmel,pmecc-lookup-table-offset = <0x0 0x8000>; + status = "disabled"; + + nfc@70000000 { + compatible = "atmel,sama5d3-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = < + 0x70000000 0x08000000 /* NFC Command Registers */ + 0xffffc000 0x00000070 /* NFC HSMC regs */ + 0x00200000 0x00100000 /* NFC SRAM banks */ + >; + clocks = <&hsmc_clk>; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d31.dtsi b/arch/arm/dts/sama5d31.dtsi new file mode 100644 index 0000000..883878b --- /dev/null +++ b/arch/arm/dts/sama5d31.dtsi @@ -0,0 +1,16 @@ +/* + * sama5d31.dtsi - Device Tree Include file for SAMA5D31 SoC + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d31ek.dts b/arch/arm/dts/sama5d31ek.dts new file mode 100644 index 0000000..988f865 --- /dev/null +++ b/arch/arm/dts/sama5d31ek.dts @@ -0,0 +1,56 @@ +/* + * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d31.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D31-EK"; + compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + leds { + d3 { + label = "d3"; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d33.dtsi b/arch/arm/dts/sama5d33.dtsi new file mode 100644 index 0000000..4b4434a --- /dev/null +++ b/arch/arm/dts/sama5d33.dtsi @@ -0,0 +1,14 @@ +/* + * sama5d33.dtsi - Device Tree Include file for SAMA5D33 SoC + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_gmac.dtsi" + +/ { + compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d33ek.dts b/arch/arm/dts/sama5d33ek.dts new file mode 100644 index 0000000..a2aff7a --- /dev/null +++ b/arch/arm/dts/sama5d33ek.dts @@ -0,0 +1,49 @@ +/* + * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d33.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D33-EK"; + compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d34.dtsi b/arch/arm/dts/sama5d34.dtsi new file mode 100644 index 0000000..aa01573 --- /dev/null +++ b/arch/arm/dts/sama5d34.dtsi @@ -0,0 +1,16 @@ +/* + * sama5d34.dtsi - Device Tree Include file for SAMA5D34 SoC + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_mci2.dtsi" + +/ { + compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d34ek.dts b/arch/arm/dts/sama5d34ek.dts new file mode 100644 index 0000000..556ba65 --- /dev/null +++ b/arch/arm/dts/sama5d34ek.dts @@ -0,0 +1,66 @@ +/* + * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d34.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D34-EK"; + compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + + 24c256@50 { + compatible = "24c256"; + reg = <0x50>; + pagesize = <64>; + }; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + }; + }; + + leds { + d3 { + label = "d3"; + gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d35.dtsi b/arch/arm/dts/sama5d35.dtsi new file mode 100644 index 0000000..16c39f4 --- /dev/null +++ b/arch/arm/dts/sama5d35.dtsi @@ -0,0 +1,18 @@ +/* + * sama5d35.dtsi - Device Tree Include file for SAMA5D35 SoC + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_uart.dtsi" +#include "sama5d3_tcb1.dtsi" + +/ { + compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d35ek.dts b/arch/arm/dts/sama5d35ek.dts new file mode 100644 index 0000000..4e37cfd --- /dev/null +++ b/arch/arm/dts/sama5d35ek.dts @@ -0,0 +1,59 @@ +/* + * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d35.dtsi" +#include "sama5d3xmb.dtsi" + +/ { + model = "Atmel SAMA5D35-EK"; + compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + isi: isi@f0034000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/dts/sama5d36.dtsi b/arch/arm/dts/sama5d36.dtsi new file mode 100644 index 0000000..e85139e --- /dev/null +++ b/arch/arm/dts/sama5d36.dtsi @@ -0,0 +1,20 @@ +/* + * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu <josh.wu@atmel.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_tcb1.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/dts/sama5d36ek.dts b/arch/arm/dts/sama5d36ek.dts new file mode 100644 index 0000000..1fa7989 --- /dev/null +++ b/arch/arm/dts/sama5d36ek.dts @@ -0,0 +1,57 @@ +/* + * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu <josh.wu@atmel.com> + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D36-EK"; + compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d36ek_cmp.dts b/arch/arm/dts/sama5d36ek_cmp.dts new file mode 100644 index 0000000..be41490 --- /dev/null +++ b/arch/arm/dts/sama5d36ek_cmp.dts @@ -0,0 +1,55 @@ +/* + * sama5d36ek_cmp.dts - Device Tree file for SAMA5D36-EK CMP board + * + * Copyright (C) 2016 Atmel, + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include "sama5d3xmb_cmp.dtsi" + +/ { + model = "Atmel SAMA5D36-EK"; + compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + aliases { + spi0 = &spi0; + }; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/sama5d3_can.dtsi b/arch/arm/dts/sama5d3_can.dtsi new file mode 100644 index 0000000..177f088 --- /dev/null +++ b/arch/arm/dts/sama5d3_can.dtsi @@ -0,0 +1,74 @@ +/* + * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with + * CAN support + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ + AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ + AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ + }; + }; + + }; + + pmc: pmc@fffffc00 { + periphck { + can0_clk: can0_clk@40 { + #clock-cells = <0>; + reg = <40>; + atmel,clk-output-range = <0 66000000>; + }; + + can1_clk: can1_clk@41 { + #clock-cells = <0>; + reg = <41>; + atmel,clk-output-range = <0 66000000>; + }; + }; + }; + + can0: can@f000c000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf000c000 0x300>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8010000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8010000 0x300>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_emac.dtsi b/arch/arm/dts/sama5d3_emac.dtsi new file mode 100644 index 0000000..b654e50 --- /dev/null +++ b/arch/arm/dts/sama5d3_emac.dtsi @@ -0,0 +1,55 @@ +/* + * sama5d3_emac.dtsi - Device Tree Include file for SAMA5D3 SoC with + * Ethernet. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */ + AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */ + AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + macb1_clk: macb1_clk@35 { + #clock-cells = <0>; + reg = <35>; + }; + }; + }; + + macb1: ethernet@f802c000 { + compatible = "cdns,at91sam9260-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_gmac.dtsi b/arch/arm/dts/sama5d3_gmac.dtsi new file mode 100644 index 0000000..81f6367 --- /dev/null +++ b/arch/arm/dts/sama5d3_gmac.dtsi @@ -0,0 +1,88 @@ +/* + * sama5d3_gmac.dtsi - Device Tree Include file for SAMA5D3 SoC with + * Gigabit Ethernet. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + macb0 { + pinctrl_macb0_data_rgmii: macb0_data_rgmii { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */ + }; + pinctrl_macb0_data_gmii: macb0_data_gmii { + atmel,pins = + <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */ + AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ + AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ + AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ + AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ + AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */ + AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */ + AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */ + }; + pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { + atmel,pins = + <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */ + }; + pinctrl_macb0_signal_gmii: macb0_signal_gmii { + atmel,pins = + <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */ + AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */ + AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */ + AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */ + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */ + AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */ + }; + + }; + }; + + pmc: pmc@fffffc00 { + periphck { + macb0_clk: macb0_clk@34 { + #clock-cells = <0>; + reg = <34>; + }; + }; + }; + + macb0: ethernet@f0028000 { + compatible = "atmel,sama5d3-gem"; + reg = <0xf0028000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_lcd.dtsi b/arch/arm/dts/sama5d3_lcd.dtsi new file mode 100644 index 0000000..14d7c2b --- /dev/null +++ b/arch/arm/dts/sama5d3_lcd.dtsi @@ -0,0 +1,215 @@ +/* + * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with + * LCD support + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + ahb { + apb { + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + pinctrl@fffff200 { + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ + AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ + }; + + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ + }; + + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ + }; + + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ + }; + + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* LCDD17 pin */ + }; + + pinctrl_lcd_rgb888: lcd-rgb-3 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + + pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD17 pin */ + AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + lcdc_clk: lcdc_clk@36 { + #clock-cells = <0>; + reg = <36>; + }; + }; + + systemck { + lcdck: lcdck@3 { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_mci2.dtsi b/arch/arm/dts/sama5d3_mci2.dtsi new file mode 100644 index 0000000..2d289ed --- /dev/null +++ b/arch/arm/dts/sama5d3_mci2.dtsi @@ -0,0 +1,59 @@ +/* + * sama5d3_mci2.dtsi - Device Tree Include file for SAMA5D3 SoC with + * 3 MMC ports + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/at91.h> + +/ { + ahb { + apb { + pinctrl@fffff200 { + mmc2 { + pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { + atmel,pins = + <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */ + }; + pinctrl_mmc2_dat1_3: mmc2_dat1_3 { + atmel,pins = + <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ + AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + mci2_clk: mci2_clk@23 { + #clock-cells = <0>; + reg = <23>; + }; + }; + }; + + mmc2: mmc@f8004000 { + compatible = "atmel,hsmci"; + reg = <0xf8004000 0x600>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; + clocks = <&mci2_clk>; + clock-names = "mci_clk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_tcb1.dtsi b/arch/arm/dts/sama5d3_tcb1.dtsi new file mode 100644 index 0000000..5be60b4 --- /dev/null +++ b/arch/arm/dts/sama5d3_tcb1.dtsi @@ -0,0 +1,39 @@ +/* + * sama5d3_tcb1.dtsi - Device Tree Include file for SAMA5D3 SoC with + * 2 TC blocks. + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/at91.h> + +/ { + aliases { + tcb1 = &tcb1; + }; + + ahb { + apb { + pmc: pmc@fffffc00 { + periphck { + tcb1_clk: tcb1_clk@27 { + #clock-cells = <0>; + reg = <27>; + }; + }; + }; + + tcb1: timer@f8014000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8014000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3_uart.dtsi b/arch/arm/dts/sama5d3_uart.dtsi new file mode 100644 index 0000000..6a547fd --- /dev/null +++ b/arch/arm/dts/sama5d3_uart.dtsi @@ -0,0 +1,79 @@ +/* + * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with + * UART support + * + * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> + * + * Licensed under GPLv2. + */ + +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/at91.h> + +/ { + aliases { + serial5 = &uart0; + serial6 = &uart1; + }; + + ahb { + apb { + pinctrl@fffff200 { + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ + AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ + AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ + }; + }; + }; + + pmc: pmc@fffffc00 { + periphck { + uart0_clk: uart0_clk@16 { + #clock-cells = <0>; + reg = <16>; + atmel,clk-output-range = <0 66000000>; + }; + + uart1_clk: uart1_clk@17 { + #clock-cells = <0>; + reg = <17>; + atmel,clk-output-range = <0 66000000>; + }; + }; + }; + + uart0: serial@f0024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0024000 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + uart1: serial@f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x200>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3xcm.dtsi b/arch/arm/dts/sama5d3xcm.dtsi new file mode 100644 index 0000000..2cf9c36 --- /dev/null +++ b/arch/arm/dts/sama5d3xcm.dtsi @@ -0,0 +1,123 @@ +/* + * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * Licensed under GPLv2 or later. + */ + +/ { + compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + }; + }; + + nand0: nand@60000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + d2 { + label = "d2"; + gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3xcm_cmp.dtsi b/arch/arm/dts/sama5d3xcm_cmp.dtsi new file mode 100644 index 0000000..77638c3 --- /dev/null +++ b/arch/arm/dts/sama5d3xcm_cmp.dtsi @@ -0,0 +1,166 @@ +/* + * sama5d3xcm_cmp.dtsi - Device Tree Include file for SAMA5D36 CMP CPU Module + * + * Copyright (C) 2016 Atmel, + * + * Licensed under GPLv2 or later. + */ + +/ { + compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + spi0: spi@f0004000 { + cs-gpios = <&pioD 13 0>, <0>, <0>, <0>; + }; + + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + }; + + i2c1: i2c@f0018000 { + pmic: act8865@5b { + compatible = "active-semi,act8865"; + reg = <0x5b>; + status = "disabled"; + + regulators { + vcc_1v8_reg: DCDC_REG1 { + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_1v2_reg: DCDC_REG2 { + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + vcc_3v3_reg: DCDC_REG3 { + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddana_reg: LDO_REG1 { + regulator-name = "VDDANA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vddfuse_reg: LDO_REG2 { + regulator-name = "FUSE_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + }; + }; + }; + }; + + nand0: nand@60000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + d2 { + label = "d2"; + gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3xdm.dtsi b/arch/arm/dts/sama5d3xdm.dtsi new file mode 100644 index 0000000..035ab72 --- /dev/null +++ b/arch/arm/dts/sama5d3xdm.dtsi @@ -0,0 +1,41 @@ +/* + * sama5d3dm.dtsi - Device Tree file for SAMA5 display module + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + i2c1: i2c@f0018000 { + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioE>; + interrupts = <31 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; + }; + }; + + adc0: adc@f8018000 { + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff200 { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pull up deglith */ + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d3xmb.dtsi b/arch/arm/dts/sama5d3xmb.dtsi new file mode 100644 index 0000000..f9ef905 --- /dev/null +++ b/arch/arm/dts/sama5d3xmb.dtsi @@ -0,0 +1,234 @@ +/* + * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3xcm.dtsi" + +/ { + compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &dbgu; + }; + + ahb { + apb { + mmc0: mmc@f0000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + status = "okay"; + u-boot,dm-pre-reloc; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + }; + + spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + u-boot,dm-pre-reloc; + + spi_flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + u-boot,dm-pre-reloc; + }; + }; + + ssc0: ssc@f0008000 { + atmel,clk-from-rk-pin; + }; + + /* + * i2c0 conflicts with ISI: + * disable it to allow the use of ISI + * can not enable audio when i2c0 disabled + */ + i2c0: i2c@f0014000 { + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck0>; + clock-names = "mclk"; + }; + }; + + i2c1: i2c@f0018000 { + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + /* use pck1 for the master clock of ov2640 */ + clocks = <&pck1>; + clock-names = "xvclk"; + assigned-clocks = <&pck1>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + isi: isi@f0034000 { + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + + mmc1: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + u-boot,dm-pre-reloc; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; + }; + }; + + adc0: adc@f8018000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + /*interrupt-parent = <&pioE>;*/ + /*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/ + reg = <1>; + }; + }; + + pinctrl@fffff200 { + board { + u-boot,dm-pre-reloc; + pinctrl_mmc0_cd: mmc0_cd { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */ + }; + + pinctrl_mmc1_cd: mmc1_cd { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */ + }; + + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */ + }; + + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */ + }; + }; + }; + + dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ + status = "okay"; + u-boot,dm-pre-reloc; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb0: gadget@00500000 { + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00600000 { + num-ports = <3>; + atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH + &pioD 26 GPIO_ACTIVE_LOW + &pioD 27 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@00700000 { + status = "okay"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D3EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/sama5d3xmb_cmp.dtsi b/arch/arm/dts/sama5d3xmb_cmp.dtsi new file mode 100644 index 0000000..77f989c --- /dev/null +++ b/arch/arm/dts/sama5d3xmb_cmp.dtsi @@ -0,0 +1,236 @@ +/* + * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board + * + * Copyright (C) 2016 Atmel, + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3xcm_cmp.dtsi" + +/ { + compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &dbgu; + }; + + ahb { + apb { + mmc0: mmc@f0000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + }; + + spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + + spi_flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + ssc0: ssc@f0008000 { + atmel,clk-from-rk-pin; + }; + + /* + * i2c0 conflicts with ISI: + * disable it to allow the use of ISI + * can not enable audio when i2c0 disabled + */ + i2c0: i2c@f0014000 { + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + clocks = <&pck0>; + clock-names = "mclk"; + }; + }; + + i2c1: i2c@f0018000 { + ov2640: camera@0x30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; + resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + /* use pck1 for the master clock of ov2640 */ + clocks = <&pck1>; + clock-names = "xvclk"; + assigned-clocks = <&pck1>; + assigned-clock-rates = <25000000>; + + port { + ov2640_0: endpoint { + remote-endpoint = <&isi_0>; + bus-width = <8>; + }; + }; + }; + }; + + usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + isi: isi@f0034000 { + port { + isi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; + + mmc1: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>; + }; + }; + + adc0: adc@f8018000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@1 { + /*interrupt-parent = <&pioE>;*/ + /*interrupts = <30 IRQ_TYPE_EDGE_FALLING>;*/ + reg = <1>; + }; + }; + + pinctrl@fffff200 { + board { + pinctrl_gpio_keys: gpio_keys { + atmel,pins = + <AT91_PIOE 27 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */ + }; + + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */ + }; + + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */ + }; + + pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { + atmel,pins = + <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ + }; + + pinctrl_sensor_reset: sensor_reset-0 { + atmel,pins = + <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */ + }; + + pinctrl_sensor_power: sensor_power-0 { + atmel,pins = + <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */ + }; + }; + }; + + dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ + status = "okay"; + u-boot,dm-pre-reloc; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb0: gadget@00500000 { + atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + }; + + sound { + compatible = "atmel,asoc-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D3EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Mic", "MICBIAS", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + + status = "disabled"; + }; + + /* Conflict with LCD pins */ + gpio_keys { + compatible = "gpio-keys"; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 27 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + }; +}; diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi new file mode 100644 index 0000000..c6512ae --- /dev/null +++ b/arch/arm/dts/sama5d4.dtsi @@ -0,0 +1,1935 @@ +/* + * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/at91.h> +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Atmel SAMA5D4 family SoC"; + compatible = "atmel,sama5d4"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &usart3; + serial1 = &usart4; + serial2 = &usart2; + serial3 = &usart0; + serial4 = &usart1; + serial5 = &uart0; + serial6 = &uart1; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + pwm0 = &pwm0; + ssc0 = &ssc0; + ssc1 = &ssc1; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + ns_sram: sram@00210000 { + compatible = "mmio-sram"; + reg = <0x00210000 0x10000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + usb0: gadget@00400000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,sama5d3-udc"; + reg = <0x00400000 0x100000 + 0xfc02c000 0x4000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep0: endpoint@0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1: endpoint@1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2: endpoint@2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3: endpoint@3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep4: endpoint@4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep5: endpoint@5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6: endpoint@6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep7: endpoint@7 { + reg = <7>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep8: endpoint@8 { + reg = <8>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep9: endpoint@9 { + reg = <9>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep10: endpoint@10 { + reg = <10>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep11: endpoint@11 { + reg = <11>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep12: endpoint@12 { + reg = <12>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep13: endpoint@13 { + reg = <13>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep14: endpoint@14 { + reg = <14>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep15: endpoint@15 { + reg = <15>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + }; + + usb1: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@00600000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00600000 0x100000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + L2: cache-controller@00a00000 { + compatible = "arm,pl310-cache"; + reg = <0x00a00000 0x1000>; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; + cache-unified; + cache-level = <2>; + }; + + nand0: nand@80000000 { + compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = < 0x80000000 0x08000000 /* EBI CS3 */ + 0xfc05c070 0x00000490 /* SMC PMECC regs */ + 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ + >; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + status = "disabled"; + + nfc@90000000 { + compatible = "atmel,sama5d3-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = < + 0x90000000 0x08000000 /* NFC Command Registers */ + 0xfc05c000 0x00000070 /* NFC HSMC regs */ + 0x00100000 0x00100000 /* NFC SRAM banks */ + >; + clocks = <&hsmc_clk>; + atmel,write-by-sram; + }; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + hlcdc: hlcdc@f0000000 { + compatible = "atmel,sama5d4-hlcdc"; + reg = <0xf0000000 0x4000>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + }; + + dma1: dma-controller@f0004000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0004000 0x200>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; + }; + + isi: isi@f0008000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0008000 0x4000>; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi_data_0_7>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + status = "disabled"; + port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + ramc0: ramc@f0010000 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xf0010000 0x200>; + clocks = <&ddrck>, <&mpddr_clk>; + clock-names = "ddrck", "mpddr"; + }; + + dma0: dma-controller@f0014000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0014000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + pmc: pmc@f0018000 { + compatible = "atmel,sama5d3-pmc", "syscon"; + reg = <0xf0018000 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + u-boot,dm-pre-reloc; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <100000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc &main_osc>; + u-boot,dm-pre-reloc; + }; + + plla: pllack@0 { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <12000000 12000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKU>; + clocks = <&main>; + u-boot,dm-pre-reloc; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <125000000 200000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + h32ck: h32mxck { + #clock-cells = <0>; + compatible = "atmel,sama5d4-clk-h32mx"; + clocks = <&mck>; + u-boot,dm-pre-reloc; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog@0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog@1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: prog@2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + ddrck: ddrck@2 { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + lcdck: lcdck@3 { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + + smdck: smdck@4 { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpcki@6 { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck@7 { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0@8 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1@9 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2@10 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + }; + + periph32ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&h32ck>; + u-boot,dm-pre-reloc; + + pioD_clk: pioD_clk@5 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <5>; + }; + + usart0_clk: usart0_clk@6 { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk@7 { + #clock-cells = <0>; + reg = <7>; + }; + + icm_clk: icm_clk@9 { + #clock-cells = <0>; + reg = <9>; + }; + + aes_clk: aes_clk@12 { + #clock-cells = <0>; + reg = <12>; + }; + + tdes_clk: tdes_clk@14 { + #clock-cells = <0>; + reg = <14>; + }; + + sha_clk: sha_clk@15 { + #clock-cells = <0>; + reg = <15>; + }; + + matrix1_clk: matrix1_clk@17 { + #clock-cells = <0>; + reg = <17>; + }; + + hsmc_clk: hsmc_clk@22 { + #clock-cells = <0>; + reg = <22>; + }; + + pioA_clk: pioA_clk@23 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <23>; + }; + + pioB_clk: pioB_clk@24 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <24>; + }; + + pioC_clk: pioC_clk@25 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <25>; + }; + + pioE_clk: pioE_clk@26 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <26>; + }; + + uart0_clk: uart0_clk@27 { + #clock-cells = <0>; + reg = <27>; + }; + + uart1_clk: uart1_clk@28 { + #clock-cells = <0>; + reg = <28>; + }; + + usart2_clk: usart2_clk@29 { + #clock-cells = <0>; + reg = <29>; + }; + + usart3_clk: usart3_clk@30 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <30>; + }; + + usart4_clk: usart4_clk@31 { + #clock-cells = <0>; + reg = <31>; + }; + + twi0_clk: twi0_clk@32 { + reg = <32>; + #clock-cells = <0>; + }; + + twi1_clk: twi1_clk@33 { + #clock-cells = <0>; + reg = <33>; + }; + + twi2_clk: twi2_clk@34 { + #clock-cells = <0>; + reg = <34>; + }; + + mci0_clk: mci0_clk@35 { + #clock-cells = <0>; + reg = <35>; + }; + + mci1_clk: mci1_clk@36 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <36>; + }; + + spi0_clk: spi0_clk@37 { + u-boot,dm-pre-reloc; + #clock-cells = <0>; + reg = <37>; + }; + + spi1_clk: spi1_clk@38 { + #clock-cells = <0>; + reg = <38>; + }; + + spi2_clk: spi2_clk@39 { + #clock-cells = <0>; + reg = <39>; + }; + + tcb0_clk: tcb0_clk@40 { + #clock-cells = <0>; + reg = <40>; + }; + + tcb1_clk: tcb1_clk@41 { + #clock-cells = <0>; + reg = <41>; + }; + + tcb2_clk: tcb2_clk@42 { + #clock-cells = <0>; + reg = <42>; + }; + + pwm_clk: pwm_clk@43 { + #clock-cells = <0>; + reg = <43>; + }; + + adc_clk: adc_clk@44 { + #clock-cells = <0>; + reg = <44>; + }; + + dbgu_clk: dbgu_clk@45 { + #clock-cells = <0>; + reg = <45>; + }; + + uhphs_clk: uhphs_clk@46 { + #clock-cells = <0>; + reg = <46>; + }; + + udphs_clk: udphs_clk@47 { + #clock-cells = <0>; + reg = <47>; + }; + + ssc0_clk: ssc0_clki@48 { + #clock-cells = <0>; + reg = <48>; + }; + + ssc1_clk: ssc1_clk@49 { + #clock-cells = <0>; + reg = <49>; + }; + + trng_clk: trng_clk@53 { + #clock-cells = <0>; + reg = <53>; + }; + + macb0_clk: macb0_clk@54 { + #clock-cells = <0>; + reg = <54>; + }; + + macb1_clk: macb1_clk@55 { + #clock-cells = <0>; + reg = <55>; + }; + + fuse_clk: fuse_clk@57 { + #clock-cells = <0>; + reg = <57>; + }; + + securam_clk: securam_clk@59 { + #clock-cells = <0>; + reg = <59>; + }; + + smd_clk: smd_clk@61 { + #clock-cells = <0>; + reg = <61>; + }; + + twi3_clk: twi3_clk@62 { + #clock-cells = <0>; + reg = <62>; + }; + + catb_clk: catb_clk@63 { + #clock-cells = <0>; + reg = <63>; + }; + }; + + periph64ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + dma0_clk: dma0_clk@8 { + #clock-cells = <0>; + reg = <8>; + }; + + cpkcc_clk: cpkcc_clk@10 { + #clock-cells = <0>; + reg = <10>; + }; + + aesb_clk: aesb_clk@13 { + #clock-cells = <0>; + reg = <13>; + }; + + mpddr_clk: mpddr_clk@16 { + #clock-cells = <0>; + reg = <16>; + }; + + matrix0_clk: matrix0_clk@18 { + #clock-cells = <0>; + reg = <18>; + }; + + vdec_clk: vdec_clk@19 { + #clock-cells = <0>; + reg = <19>; + }; + + dma1_clk: dma1_clk@50 { + #clock-cells = <0>; + reg = <50>; + }; + + lcdc_clk: lcdc_clk@51 { + #clock-cells = <0>; + reg = <51>; + }; + + isi_clk: isi_clk@52 { + #clock-cells = <0>; + reg = <52>; + }; + }; + }; + + mmc0: mmc@f8000000 { + compatible = "atmel,hsmci"; + reg = <0xf8000000 0x600>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(0))>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + }; + + uart0: serial@f8004000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8004000 0x100>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(22))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc0: ssc@f8008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf8008000 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(26))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&ssc0_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + pwm0: pwm@f800c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf800c000 0x300>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + status = "disabled"; + }; + + spi0: spi@f8010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8010000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(10))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + i2c0: i2c@f8014000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8014000 0x4000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(2))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + i2c1: i2c@f8018000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8018000 0x4000>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(4))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + + tcb0: timer@f801c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf801c000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + macb0: ethernet@f8020000 { + compatible = "atmel,sama5d4-gem"; + reg = <0xf8020000 0x100>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + i2c2: i2c@f8024000 { + compatible = "atmel,sama5d4-i2c"; + reg = <0xf8024000 0x4000>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(6))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi2_clk>; + status = "disabled"; + }; + + sfr: sfr@f8028000 { + compatible = "atmel,sama5d4-sfr", "syscon"; + reg = <0xf8028000 0x60>; + }; + + usart0: serial@f802c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf802c000 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; + clocks = <&usart0_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart1: serial@f8030000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8030000 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; + clocks = <&usart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + mmc1: mmc@fc000000 { + compatible = "atmel,hsmci"; + reg = <0xfc000000 0x600>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(1))>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; + }; + + uart1: serial@fc004000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc004000 0x100>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(24))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart2: serial@fc008000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc008000 0x100>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(16))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fc00c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc00c000 0x100>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(18))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart4: serial@fc010000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc010000 0x100>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(20))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart4>; + clocks = <&usart4_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + ssc1: ssc@fc014000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xfc014000 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(28))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&ssc1_clk>; + clock-names = "pclk"; + status = "disabled"; + }; + + spi1: spi@fc018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc018000 0x100>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(12))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + spi2: spi@fc01c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc01c000 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(14))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + clocks = <&spi2_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + tcb1: timer@fc020000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xfc020000 0x100>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + }; + + macb1: ethernet@fc028000 { + compatible = "atmel,sama5d4-gem"; + reg = <0xfc028000 0x100>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + trng@fc030000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xfc030000 0x100>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&trng_clk>; + }; + + adc0: adc@fc034000 { + compatible = "atmel,at91sam9x5-adc"; + reg = <0xfc034000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0x01f>; + atmel,adc-startup-time = <40>; + atmel,adc-use-external-triggers; + atmel,adc-vref = <3000>; + atmel,adc-res = <8 10>; + atmel,adc-sample-hold-time = <11>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-ts-pressure-threshold = <10000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + trigger@0 { + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + reg = <0>; + }; + trigger@1 { + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + reg = <1>; + }; + trigger@2 { + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + reg = <2>; + }; + trigger@3 { + trigger-name = "continuous"; + trigger-value = <0x6>; + reg = <3>; + }; + }; + + aes@fc044000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xfc044000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(41))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(40))>; + dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; + status = "okay"; + }; + + tdes@fc04c000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xfc04c000 0x100>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(42))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(43))>; + dma-names = "tx", "rx"; + clocks = <&tdes_clk>; + clock-names = "tdes_clk"; + status = "okay"; + }; + + sha@fc050000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xfc050000 0x100>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(44))>; + dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; + status = "okay"; + }; + + rstc@fc068600 { + compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; + reg = <0xfc068600 0x10>; + clocks = <&clk32k>; + }; + + shdwc@fc068610 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfc068610 0x10>; + clocks = <&clk32k>; + }; + + pit: timer@fc068630 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfc068630 0x10>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&h32ck>; + }; + + watchdog@fc068640 { + compatible = "atmel,sama5d4-wdt"; + reg = <0xfc068640 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + sckc@fc068650 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfc068650 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <250000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + rtc@fc0686b0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfc0686b0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + }; + + dbgu: serial@fc069000 { + compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfc069000 0x200>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&dbgu_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + pioA: gpio@fc06a000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06a000 0x100>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fc06b000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06b000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fc06c000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06c000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + u-boot,dm-pre-reloc; + }; + + pioD: gpio@fc068000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc068000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + }; + + pioE: gpio@fc06d000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06d000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + }; + + pinctrl@fc06a000 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfc068000 0xfc068000 0x100 + 0xfc06a000 0xfc06a000 0x4000>; + /* WARNING: revisit as pin spec has changed */ + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ + 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ + 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ + 0x0003ff00 0x8002a800 0x00000000 /* pioD */ + 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ + >; + reg = < 0xfc06a000 0x100 + 0xfc06b000 0x100 + 0xfc06c000 0x100 + 0xfc068000 0x100 + 0xfc06d000 0x100 + >; + + /* pinctrl pin settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = + <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = + <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = + <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = + <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */ + <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */ + AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */ + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ + AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ + }; + }; + + isi { + pinctrl_isi_data_0_7: isi-0-data-0-7 { + atmel,pins = + <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */ + AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */ + AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */ + AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */ + AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */ + AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */ + AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */ + AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */ + AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */ + AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */ + AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */ + }; + pinctrl_isi_data_8_9: isi-0-data-8-9 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */ + AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ + }; + pinctrl_isi_data_10_11: isi-0-data-10-11 { + atmel,pins = + <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */ + AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ + }; + }; + + lcd { + pinctrl_lcd_base: lcd-base-0 { + atmel,pins = + <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ + AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ + AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ + AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ + }; + pinctrl_lcd_pwm: lcd-pwm-0 { + atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ + }; + pinctrl_lcd_rgb444: lcd-rgb-0 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ + }; + pinctrl_lcd_rgb565: lcd-rgb-1 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ + }; + pinctrl_lcd_rgb666: lcd-rgb-2 { + atmel,pins = + <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb777: lcd-rgb-3 { + atmel,pins = + /* LCDDAT0 conflicts with TMS */ + <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + /* LCDDAT8 conflicts with TCK */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + /* LCDDAT16 conflicts with NTRST */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + pinctrl_lcd_rgb888: lcd-rgb-4 { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ + AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ + AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ + AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ + AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ + AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ + AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ + AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ + AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ + AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ + AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ + AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ + AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ + AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ + AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ + AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ + AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ + AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ + AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ + AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ + AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ + AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ + AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ + >; + }; + }; + + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */ + AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */ + AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */ + AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */ + AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */ + AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */ + AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */ + AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */ + AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */ + AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */ + >; + }; + }; + + mmc0 { + pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { + atmel,pins = + <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ + AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */ + AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */ + >; + }; + pinctrl_mmc0_dat1_3: mmc0_dat1_3 { + atmel,pins = + <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */ + AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */ + AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */ + >; + }; + pinctrl_mmc0_dat4_7: mmc0_dat4_7 { + atmel,pins = + <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */ + AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */ + AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */ + AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */ + >; + }; + }; + + mmc1 { + u-boot,dm-pre-reloc; + pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ + AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ + AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ + >; + }; + pinctrl_mmc1_dat1_3: mmc1_dat1_3 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ + AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ + AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ + >; + }; + }; + + nand0 { + pinctrl_nand: nand-0 { + atmel,pins = + <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ + + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ + + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ + }; + }; + + spi0 { + u-boot,dm-pre-reloc; + pinctrl_spi0: spi0-0 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ + >; + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */ + AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */ + AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */ + AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */ + AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */ + AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */ + AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */ + AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */ + AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */ + AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */ + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */ + >; + }; + }; + + spi2 { + pinctrl_spi2: spi2-0 { + atmel,pins = + <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */ + AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */ + AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */ + >; + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ + AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ + >; + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE /* RXD */ + AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* TXD */ + >; + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */ + AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */ + >; + }; + pinctrl_usart0_rts: usart0_rts-0 { + atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_usart0_cts: usart0_cts-0 { + atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */ + AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */ + >; + }; + pinctrl_usart1_rts: usart1_rts-0 { + atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_usart1_cts: usart1_cts-0 { + atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */ + >; + }; + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ + }; + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ + }; + }; + + usart3 { + u-boot,dm-pre-reloc; + pinctrl_usart3: usart3-0 { + u-boot,dm-pre-reloc; + atmel,pins = + <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ + AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ + >; + }; + }; + + usart4 { + pinctrl_usart4: usart4-0 { + atmel,pins = + <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ + AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ + >; + }; + pinctrl_usart4_rts: usart4_rts-0 { + atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ + }; + pinctrl_usart4_cts: usart4_cts-0 { + atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ + }; + }; + }; + + aic: interrupt-controller@fc06e000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d4-aic"; + interrupt-controller; + reg = <0xfc06e000 0x200>; + atmel,external-irqs = <56>; + }; + }; + }; +}; diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c index a03abfc..28c8cf2 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c @@ -18,45 +18,45 @@ unsigned int has_lcdc() void at91_serial0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */ at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */ at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */ at91_periph_clk_enable(ATMEL_ID_USART2); } void at91_serial3_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */ at91_periph_clk_enable(ATMEL_ID_USART3); } void at91_seriald_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_periph_clk_enable(ATMEL_ID_SYS); } #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ at91_periph_clk_enable(ATMEL_ID_SPI0); @@ -72,9 +72,9 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ - at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ - at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ at91_periph_clk_enable(ATMEL_ID_SPI1); @@ -91,12 +91,12 @@ void at91_spi1_hw_init(unsigned long cs_mask) void at91_mci_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */ - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */ at91_periph_clk_enable(ATMEL_ID_HSMCI0); } @@ -104,37 +104,37 @@ void at91_mci_hw_init(void) #ifdef CONFIG_LCD void at91_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */ - at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ - at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */ - - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */ + + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ at91_periph_clk_enable(ATMEL_ID_LCDC); } diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index 3e4555a..8de086e 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -64,32 +64,32 @@ char *get_cpu_name() void at91_seriald_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ at91_periph_clk_enable(ATMEL_ID_SYS); } void at91_serial0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ at91_periph_clk_enable(ATMEL_ID_USART0); } void at91_serial1_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ at91_periph_clk_enable(ATMEL_ID_USART1); } void at91_serial2_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ at91_periph_clk_enable(ATMEL_ID_USART2); } @@ -97,12 +97,12 @@ void at91_serial2_hw_init(void) void at91_mci_hw_init(void) { /* Initialize the MCI0 */ - at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */ - at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ at91_periph_clk_enable(ATMEL_ID_HSMCI0); } @@ -110,20 +110,20 @@ void at91_mci_hw_init(void) #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ at91_periph_clk_enable(ATMEL_ID_SPI0); if (cs_mask & (1 << 0)) - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); if (cs_mask & (1 << 1)) - at91_set_b_periph(AT91_PIO_PORTA, 7, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 7, 0); if (cs_mask & (1 << 2)) - at91_set_b_periph(AT91_PIO_PORTA, 1, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 1, 0); if (cs_mask & (1 << 3)) - at91_set_b_periph(AT91_PIO_PORTB, 3, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTB, 3, 0); if (cs_mask & (1 << 4)) at91_set_pio_output(AT91_PIO_PORTA, 14, 0); if (cs_mask & (1 << 5)) @@ -136,20 +136,20 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ - at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ - at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ + at91_pio3_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ at91_periph_clk_enable(ATMEL_ID_SPI1); if (cs_mask & (1 << 0)) - at91_set_b_periph(AT91_PIO_PORTA, 8, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 8, 0); if (cs_mask & (1 << 1)) - at91_set_b_periph(AT91_PIO_PORTA, 0, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 0, 0); if (cs_mask & (1 << 2)) - at91_set_b_periph(AT91_PIO_PORTA, 31, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 31, 0); if (cs_mask & (1 << 3)) - at91_set_b_periph(AT91_PIO_PORTA, 30, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTA, 30, 0); if (cs_mask & (1 << 4)) at91_set_pio_output(AT91_PIO_PORTA, 8, 0); if (cs_mask & (1 << 5)) @@ -181,45 +181,45 @@ void at91_macb_hw_init(void) /* Enable EMAC0 clock */ at91_periph_clk_enable(ATMEL_ID_EMAC0); /* EMAC0 pins setup */ - at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ } if (has_emac1()) { /* Enable EMAC1 clock */ at91_periph_clk_enable(ATMEL_ID_EMAC1); /* EMAC1 pins setup */ - at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ - at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ - at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ - at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ - at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ - at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ - at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ - at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ - at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ - at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ } #ifndef CONFIG_RMII /* Only emac0 support MII */ if (has_emac0()) { - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ } #endif } diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c index 64ac262..6becdd7 100644 --- a/arch/arm/mach-at91/armv7/sama5d3_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c @@ -52,8 +52,8 @@ char *get_cpu_name() void at91_serial0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART0); @@ -61,8 +61,8 @@ void at91_serial0_hw_init(void) void at91_serial1_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART1); @@ -70,8 +70,8 @@ void at91_serial1_hw_init(void) void at91_serial2_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */ - at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART2); @@ -79,8 +79,8 @@ void at91_serial2_hw_init(void) void at91_seriald_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */ - at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_DBGU); @@ -89,9 +89,9 @@ void at91_seriald_hw_init(void) #if defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */ if (cs_mask & (1 << 0)) at91_set_pio_output(AT91_PIO_PORTD, 13, 1); @@ -110,18 +110,18 @@ void at91_spi0_hw_init(unsigned long cs_mask) #ifdef CONFIG_GENERIC_ATMEL_MCI void at91_mci_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */ - at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */ #ifdef CONFIG_ATMEL_MCI_8BIT - at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */ - at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */ - at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */ - at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */ #endif - at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI0); @@ -131,16 +131,16 @@ void at91_mci_hw_init(void) #ifdef CONFIG_MACB void at91_macb_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_EMAC); @@ -148,23 +148,23 @@ void at91_macb_hw_init(void) void at91_gmac_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ - - at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ - - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ + + at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ + + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_GMAC); @@ -174,30 +174,30 @@ void at91_gmac_hw_init(void) #ifdef CONFIG_LCD void at91_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ /* The lower 16-bit of LCD only available on Port A */ - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_LCDC); diff --git a/arch/arm/mach-at91/armv7/u-boot-spl.lds b/arch/arm/mach-at91/armv7/u-boot-spl.lds index c667c55..d2e41a0 100644 --- a/arch/arm/mach-at91/armv7/u-boot-spl.lds +++ b/arch/arm/mach-at91/armv7/u-boot-spl.lds @@ -47,6 +47,8 @@ SECTIONS *(.__end) } >.sram + _image_binary_end = .; + .bss : { . = ALIGN(4); diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h index 3012278..4840a2b 100644 --- a/arch/arm/mach-at91/include/mach/at91_pio.h +++ b/arch/arm/mach-at91/include/mach/at91_pio.h @@ -32,6 +32,8 @@ #define AT91_ASM_PIOD_ASR \ (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) +#define PIO_SCDR_DIV 0x3fff /* Slow Clock Divider Selection for Debouncing Mask */ + #ifndef __ASSEMBLY__ typedef struct at91_port { @@ -63,28 +65,32 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; -#if defined(CPU_HAS_PIO3) - u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ - u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ - u32 reserved5[2]; - u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ - u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ - u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ - u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ - u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ - u32 ppder; /* 0x94 Pad Pull-down Enable Register */ - u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ - u32 reserved6; /* */ -#else - u32 asr; /* 0x70 Select A Register */ - u32 bsr; /* 0x74 Select B Register */ - u32 absr; /* 0x78 AB Select Status Register */ - u32 reserved5[9]; /* */ -#endif + union { + struct { + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; /* */ + } pio3; + + struct { + u32 asr; /* 0x70 Select A Register */ + u32 bsr; /* 0x74 Select B Register */ + u32 absr; /* 0x78 AB Select Status Register */ + u32 reserved5[9]; /* */ + } pio2; + } mux; + u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ u32 owsr; /* OxA8 Output Write Status Register */ -#if defined(CPU_HAS_PIO3) u32 reserved7; /* */ u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ @@ -103,10 +109,11 @@ typedef struct at91_port { u32 wpsr; /* 0xE8 Write Protect Status Register */ u32 reserved11[5]; /* */ u32 schmitt; /* 0x100 Schmitt Trigger Register */ - u32 reserved12[63]; -#else - u32 reserved6[85]; -#endif + u32 reserved12[4]; /* 0x104 ~ 0x110 */ + u32 driver1; /* 0x114 I/O Driver Register1(AT91SAM9x5's driver1) */ + u32 driver12; /* 0x118 I/O Driver Register12(AT91SAM9x5's driver2 or SAMA5D3x's driver1 ) */ + u32 driver2; /* 0x11C I/O Driver Register2(SAMA5D3x's driver2) */ + u32 reserved13[12]; /* 0x120 ~ 0x14C */ } at91_port_t; typedef union at91_pio { @@ -123,13 +130,6 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); -#if defined(CPU_HAS_PIO3) -int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); -int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); -int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); -int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); -#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); @@ -138,6 +138,15 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); int at91_set_pio_value(unsigned port, unsigned pin, int value); int at91_get_pio_value(unsigned port, unsigned pin); + +int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); +int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); #endif #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 8100ebe..e7224e4 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -171,8 +171,6 @@ * Other misc defines */ #define ATMEL_PIO_PORTS 4 -#define CPU_HAS_PIO3 -#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP #define ATMEL_ID_UHP ATMEL_ID_UHPHS diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 5a32bdb..df0f719 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -223,15 +223,13 @@ static inline unsigned pin_to_mask(unsigned pin) at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) #define at91_set_gpio_input(x, y) \ at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y) -#define at91_set_gpio_value(x, y) \ - at91_set_pio_value((x - PIN_BASE) / 32,(x % 32), y) -#define at91_get_gpio_value(x) \ - at91_get_pio_value((x - PIN_BASE) / 32,(x % 32)) -#else -#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y) -#define at91_get_gpio_value(x) at91_get_pio_value(x) #endif +#define at91_set_gpio_value(x, y) \ + at91_set_pio_value((x / 32), (x % 32), y) +#define at91_get_gpio_value(x) \ + at91_get_pio_value((x / 32), (x % 32)) + #define GPIO_PIOA_BASE (0) #define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) #define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 33f6c97..d558f95 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -188,8 +188,6 @@ * Other misc defines */ #define ATMEL_PIO_PORTS 5 -#define CPU_HAS_PIO3 -#define PIO_SCDR_DIV 0x3fff #define CPU_HAS_PCR /* Timer */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index 90085da..78cc2a7 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -174,8 +174,6 @@ * Other misc defines */ #define ATMEL_PIO_PORTS 5 -#define CPU_HAS_PIO3 -#define PIO_SCDR_DIV 0x3fff #define CPU_HAS_PCR #define CPU_HAS_H32MXDIV diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index 98f280c..e113336 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -39,12 +39,16 @@ u32 spl_boot_device(void) #if defined(CONFIG_SYS_USE_MMC) if (dev == ATMEL_SAMA5_BOOT_FROM_MCI) { +#if defined(CONFIG_SPL_OF_CONTROL) + return BOOT_DEVICE_MMC1; +#else if (off == 0) return BOOT_DEVICE_MMC1; if (off == 1) return BOOT_DEVICE_MMC2; printf("ERROR: MMC controller %i not present!\n", dev); hang(); +#endif } #endif @@ -53,6 +57,9 @@ u32 spl_boot_device(void) return BOOT_DEVICE_SPI; #endif + if (dev == ATMEL_SAMA5_BOOT_FROM_SMC) + return BOOT_DEVICE_NAND; + if (dev == ATMEL_SAMA5_BOOT_FROM_SAMBA) return BOOT_DEVICE_USB; diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 688289e..b75c2cc 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -77,6 +77,8 @@ void s_init(void) void board_init_f(ulong dummy) { + int ret; + switch_to_main_crystal_osc(); #ifdef CONFIG_SAMA5D2 @@ -99,7 +101,14 @@ void board_init_f(ulong dummy) board_early_init_f(); + mem_init(); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + preloader_console_init(); - mem_init(); } |