diff options
author | Tom Rini <trini@konsulko.com> | 2017-04-14 13:05:57 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2017-04-14 13:05:57 (GMT) |
commit | c1a16c3ab541c014b029b42cc27cae496107e170 (patch) | |
tree | e5da12851a4d920d9b79fa8547db9f479e506fed /arch | |
parent | af1b7286d8b2712cff5779d8a1565afed9d9d8e6 (diff) | |
parent | 09397d99edb402c04d1e20b32989b5b2ecbb037a (diff) | |
download | u-boot-fsl-qoriq-c1a16c3ab541c014b029b42cc27cae496107e170.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 3 | ||||
-rw-r--r-- | arch/arm/dts/socfpga_cyclone5_socdk.dts | 8 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 11 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/include/mach/boot0.h | 24 |
4 files changed, 26 insertions, 20 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts index 7d3f989..833a87d 100644 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -7,7 +7,7 @@ #include "socfpga_cyclone5.dtsi" / { - model = "DENX MCVEVK"; + model = "Aries MCVEVK"; compatible = "altr,socfpga-cyclone5", "altr,socfpga"; chosen { @@ -54,5 +54,6 @@ }; &usb1 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index d4df1a1..f175ef2 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -54,10 +54,18 @@ rxc-skew-ps = <2000>; }; +&gpio0 { + status = "okay"; +}; + &gpio1 { status = "okay"; }; +&gpio2 { + status = "okay"; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index e56b3db..9bfee04 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -43,6 +43,7 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool + select ALTERA_SDRAM choice prompt "Altera SOCFPGA board select" @@ -56,8 +57,8 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 -config TARGET_SOCFPGA_DENX_MCVEVK - bool "DENX MCVEVK (Cyclone V)" +config TARGET_SOCFPGA_ARIES_MCVEVK + bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_EBV_SOCRATES @@ -97,7 +98,7 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "is1" if TARGET_SOCFPGA_IS1 - default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK + default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 @@ -106,7 +107,7 @@ config SYS_BOARD config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK - default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO @@ -122,7 +123,7 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_is1" if TARGET_SOCFPGA_IS1 - default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK + default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h index aaada31..22d9e7f 100644 --- a/arch/arm/mach-socfpga/include/mach/boot0.h +++ b/arch/arm/mach-socfpga/include/mach/boot0.h @@ -8,21 +8,17 @@ #define __BOOT0_H #ifdef CONFIG_SPL_BUILD -#define ARM_SOC_BOOT0_HOOK \ - .balignl 64,0xf33db33f; \ - \ - .word 0x1337c0d3; /* SoCFPGA preloader validation word */ \ - .word 0xc01df00d; /* Version, flags, length */ \ - .word 0xcafec0d3; /* Checksum, zero-pad */ \ - nop; \ - \ - b reset; /* SoCFPGA jumps here */ \ - nop; \ - nop; \ + .balignl 64,0xf33db33f; + + .word 0x1337c0d3; /* SoCFPGA preloader validation word */ + .word 0xc01df00d; /* Version, flags, length */ + .word 0xcafec0d3; /* Checksum, zero-pad */ nop; -#else -#define ARM_SOC_BOOT0_HOOK -#endif + b reset; /* SoCFPGA jumps here */ + nop; + nop; + nop; +#endif #endif /* __BOOT0_H */ |