Merge branch 'master' of git://git.denx.de/u-boot-video

3 files changed, 138 insertions, 108 deletions

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index faa1479..d328df9 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -84,7 +84,8 @@ struct sunxi_ccm_reg {
 	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
 	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
 #endif
-	u32 reserved14[3];
+	u32 tve_clk_cfg;	/* 0x120 H3/H5 TVE module clock */
+	u32 reserved14[2];
 	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
 	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
 	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
@@ -307,6 +308,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_DE_BE0		12
 #define AHB_GATE_OFFSET_DE		12
 #define AHB_GATE_OFFSET_HDMI		11
+#define AHB_GATE_OFFSET_TVE		9
 #ifndef CONFIG_SUNXI_DE2
 #define AHB_GATE_OFFSET_LCD1		5
 #define AHB_GATE_OFFSET_LCD0		4
@@ -415,6 +417,9 @@ struct sunxi_ccm_reg {
 
 #define CCM_HDMI_SLOW_CTRL_DDC_GATE	(1 << 31)
 
+#define CCM_TVE_CTRL_GATE		(0x1 << 31)
+#define CCM_TVE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+
 #if defined(CONFIG_MACH_SUN50I)
 #define MBUS_CLK_DEFAULT		0x81000002 /* PLL6x2 / 3 */
 #elif defined(CONFIG_MACH_SUN8I)
@@ -448,6 +453,7 @@ struct sunxi_ccm_reg {
 #define AHB_RESET_OFFSET_DE		12
 #define AHB_RESET_OFFSET_HDMI		11
 #define AHB_RESET_OFFSET_HDMI2		10
+#define AHB_RESET_OFFSET_TVE		9
 #ifndef CONFIG_SUNXI_DE2
 #define AHB_RESET_OFFSET_LCD1		5
 #define AHB_RESET_OFFSET_LCD0		4
diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
index 93803ad..e101977 100644
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -225,52 +225,6 @@ struct sunxi_hdmi_reg {
 };
 
 /*
- * This is based on the A10s User Manual, and the A10s only supports
- * composite video and not vga like the A10 / A20 does, still other
- * than the removed vga out capability the tvencoder seems to be the same.
- * "unknown#" registers are registers which are used in the A10 kernel code,
- * but not documented in the A10s User Manual.
- */
-struct sunxi_tve_reg {
-	u32 gctrl;			/* 0x000 */
-	u32 cfg0;			/* 0x004 */
-	u32 dac_cfg0;			/* 0x008 */
-	u32 filter;			/* 0x00c */
-	u32 chroma_freq;		/* 0x010 */
-	u32 porch_num;			/* 0x014 */
-	u32 unknown0;			/* 0x018 */
-	u32 line_num;			/* 0x01c */
-	u32 blank_black_level;		/* 0x020 */
-	u32 unknown1;			/* 0x024, seems to be 1 byte per dac */
-	u8 res0[0x08];			/* 0x028 */
-	u32 auto_detect_en;		/* 0x030 */
-	u32 auto_detect_int_status;	/* 0x034 */
-	u32 auto_detect_status;		/* 0x038 */
-	u32 auto_detect_debounce;	/* 0x03c */
-	u32 csc_reg0;			/* 0x040 */
-	u32 csc_reg1;			/* 0x044 */
-	u32 csc_reg2;			/* 0x048 */
-	u32 csc_reg3;			/* 0x04c */
-	u8 res1[0xb0];			/* 0x050 */
-	u32 color_burst;		/* 0x100 */
-	u32 vsync_num;			/* 0x104 */
-	u32 notch_freq;			/* 0x108 */
-	u32 cbr_level;			/* 0x10c */
-	u32 burst_phase;		/* 0x110 */
-	u32 burst_width;		/* 0x114 */
-	u32 unknown2;			/* 0x118 */
-	u32 sync_vbi_level;		/* 0x11c */
-	u32 white_level;		/* 0x120 */
-	u32 active_num;			/* 0x124 */
-	u32 chroma_bw_gain;		/* 0x128 */
-	u32 notch_width;		/* 0x12c */
-	u32 resync_num;			/* 0x130 */
-	u32 slave_para;			/* 0x134 */
-	u32 cfg1;			/* 0x138 */
-	u32 cfg2;			/* 0x13c */
-};
-
-/*
  * DE-FE register constants.
  */
 #define SUNXI_DE_FE_WIDTH(x)			(((x) - 1) << 0)
@@ -394,67 +348,6 @@ struct sunxi_tve_reg {
 #define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE	(1 << 8)
 #define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE	(1 << 9)
 
-/*
- * TVE register constants.
- */
-#define SUNXI_TVE_GCTRL_ENABLE			(1 << 0)
-/*
- * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
- * dac from tve1. When using tve1 the mux value must be written to both tve0's
- * and tve1's gctrl reg.
- */
-#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac)	(0xf << (((dac) + 1) * 4))
-#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel)	((sel) << (((dac) + 1) * 4))
-#define SUNXI_TVE_CFG0_VGA			0x20000000
-#define SUNXI_TVE_CFG0_PAL			0x07030001
-#define SUNXI_TVE_CFG0_NTSC			0x07030000
-#define SUNXI_TVE_DAC_CFG0_VGA			0x403e1ac7
-#ifdef CONFIG_MACH_SUN5I
-#define SUNXI_TVE_DAC_CFG0_COMPOSITE		0x433f0009
-#else
-#define SUNXI_TVE_DAC_CFG0_COMPOSITE		0x403f0008
-#endif
-#define SUNXI_TVE_FILTER_COMPOSITE		0x00000120
-#define SUNXI_TVE_CHROMA_FREQ_PAL_M		0x21e6efe3
-#define SUNXI_TVE_CHROMA_FREQ_PAL_NC		0x21f69446
-#define SUNXI_TVE_PORCH_NUM_PAL			0x008a0018
-#define SUNXI_TVE_PORCH_NUM_NTSC		0x00760020
-#define SUNXI_TVE_LINE_NUM_PAL			0x00160271
-#define SUNXI_TVE_LINE_NUM_NTSC			0x0016020d
-#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL		0x00fc00fc
-#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC	0x00f0011a
-#define SUNXI_TVE_UNKNOWN1_VGA			0x00000000
-#define SUNXI_TVE_UNKNOWN1_COMPOSITE		0x18181818
-#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac)	(1 << ((dac) + 0))
-#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac)	(1 << ((dac) + 16))
-#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac)	(1 << ((dac) + 0))
-#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac)	((dac) * 8)
-#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac)	(3 << ((dac) * 8))
-#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE	0
-#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED	1
-#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND	3
-#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d)	((d) * 8)
-#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d)	(0xf << ((d) * 8))
-#define SUNXI_TVE_CSC_REG0_ENABLE		(1 << 31)
-#define SUNXI_TVE_CSC_REG0			0x08440832
-#define SUNXI_TVE_CSC_REG1			0x3b6dace1
-#define SUNXI_TVE_CSC_REG2			0x0e1d13dc
-#define SUNXI_TVE_CSC_REG3			0x00108080
-#define SUNXI_TVE_COLOR_BURST_PAL_M		0x00000000
-#define SUNXI_TVE_CBR_LEVEL_PAL			0x00002828
-#define SUNXI_TVE_CBR_LEVEL_NTSC		0x0000004f
-#define SUNXI_TVE_BURST_PHASE_NTSC		0x00000000
-#define SUNXI_TVE_BURST_WIDTH_COMPOSITE		0x0016447e
-#define SUNXI_TVE_UNKNOWN2_PAL			0x0000e0e0
-#define SUNXI_TVE_UNKNOWN2_NTSC			0x0000a0a0
-#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC		0x001000f0
-#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE		0x000005a0
-#define SUNXI_TVE_CHROMA_BW_GAIN_COMP		0x00000002
-#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE		0x00000101
-#define SUNXI_TVE_RESYNC_NUM_PAL		0x800d000c
-#define SUNXI_TVE_RESYNC_NUM_NTSC		0x000e000c
-#define SUNXI_TVE_SLAVE_PARA_COMPOSITE		0x00000000
-
 int sunxi_simplefb_setup(void *blob);
 
 #endif /* _SUNXI_DISPLAY_H */
diff --git a/arch/arm/include/asm/arch-sunxi/tve.h b/arch/arm/include/asm/arch-sunxi/tve.h
new file mode 100644
index 0000000..41a14a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/tve.h
@@ -0,0 +1,131 @@
+/*
+ * Sunxi TV encoder register and constant defines
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TVE_H
+#define _TVE_H
+
+enum tve_mode {
+	tve_mode_vga,
+	tve_mode_composite_pal,
+	tve_mode_composite_ntsc,
+	tve_mode_composite_pal_m,
+	tve_mode_composite_pal_nc,
+};
+
+/*
+ * This is based on the A10s User Manual, and the A10s only supports
+ * composite video and not vga like the A10 / A20 does, still other
+ * than the removed vga out capability the tvencoder seems to be the same.
+ * "unknown#" registers are registers which are used in the A10 kernel code,
+ * but not documented in the A10s User Manual.
+ */
+struct sunxi_tve_reg {
+	u32 gctrl;			/* 0x000 */
+	u32 cfg0;			/* 0x004 */
+	u32 dac_cfg0;			/* 0x008 */
+	u32 filter;			/* 0x00c */
+	u32 chroma_freq;		/* 0x010 */
+	u32 porch_num;			/* 0x014 */
+	u32 unknown0;			/* 0x018 */
+	u32 line_num;			/* 0x01c */
+	u32 blank_black_level;		/* 0x020 */
+	u32 unknown1;			/* 0x024, seems to be 1 byte per dac */
+	u8 res0[0x08];			/* 0x028 */
+	u32 auto_detect_en;		/* 0x030 */
+	u32 auto_detect_int_status;	/* 0x034 */
+	u32 auto_detect_status;		/* 0x038 */
+	u32 auto_detect_debounce;	/* 0x03c */
+	u32 csc_reg0;			/* 0x040 */
+	u32 csc_reg1;			/* 0x044 */
+	u32 csc_reg2;			/* 0x048 */
+	u32 csc_reg3;			/* 0x04c */
+	u8 res1[0xb0];			/* 0x050 */
+	u32 color_burst;		/* 0x100 */
+	u32 vsync_num;			/* 0x104 */
+	u32 notch_freq;			/* 0x108 */
+	u32 cbr_level;			/* 0x10c */
+	u32 burst_phase;		/* 0x110 */
+	u32 burst_width;		/* 0x114 */
+	u32 unknown2;			/* 0x118 */
+	u32 sync_vbi_level;		/* 0x11c */
+	u32 white_level;		/* 0x120 */
+	u32 active_num;			/* 0x124 */
+	u32 chroma_bw_gain;		/* 0x128 */
+	u32 notch_width;		/* 0x12c */
+	u32 resync_num;			/* 0x130 */
+	u32 slave_para;			/* 0x134 */
+	u32 cfg1;			/* 0x138 */
+	u32 cfg2;			/* 0x13c */
+};
+
+/*
+ * TVE register constants.
+ */
+#define SUNXI_TVE_GCTRL_ENABLE			(1 << 0)
+/*
+ * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
+ * dac from tve1. When using tve1 the mux value must be written to both tve0's
+ * and tve1's gctrl reg.
+ */
+#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac)	(0xf << (((dac) + 1) * 4))
+#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel)	((sel) << (((dac) + 1) * 4))
+#define SUNXI_TVE_CFG0_VGA			0x20000000
+#define SUNXI_TVE_CFG0_PAL			0x07030001
+#define SUNXI_TVE_CFG0_NTSC			0x07030000
+#define SUNXI_TVE_DAC_CFG0_VGA			0x403e1ac7
+#ifdef CONFIG_MACH_SUN5I
+#define SUNXI_TVE_DAC_CFG0_COMPOSITE		0x433f0009
+#else
+#define SUNXI_TVE_DAC_CFG0_COMPOSITE		0x403f0008
+#endif
+#define SUNXI_TVE_FILTER_COMPOSITE		0x00000120
+#define SUNXI_TVE_CHROMA_FREQ_PAL_M		0x21e6efe3
+#define SUNXI_TVE_CHROMA_FREQ_PAL_NC		0x21f69446
+#define SUNXI_TVE_PORCH_NUM_PAL			0x008a0018
+#define SUNXI_TVE_PORCH_NUM_NTSC		0x00760020
+#define SUNXI_TVE_LINE_NUM_PAL			0x00160271
+#define SUNXI_TVE_LINE_NUM_NTSC			0x0016020d
+#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL		0x00fc00fc
+#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC	0x00f0011a
+#define SUNXI_TVE_UNKNOWN1_VGA			0x00000000
+#define SUNXI_TVE_UNKNOWN1_COMPOSITE		0x18181818
+#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac)	(1 << ((dac) + 0))
+#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac)	(1 << ((dac) + 16))
+#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac)	(1 << ((dac) + 0))
+#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac)	((dac) * 8)
+#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac)	(3 << ((dac) * 8))
+#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE	0
+#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED	1
+#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND	3
+#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d)	((d) * 8)
+#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d)	(0xf << ((d) * 8))
+#define SUNXI_TVE_CSC_REG0_ENABLE		(1 << 31)
+#define SUNXI_TVE_CSC_REG0			0x08440832
+#define SUNXI_TVE_CSC_REG1			0x3b6dace1
+#define SUNXI_TVE_CSC_REG2			0x0e1d13dc
+#define SUNXI_TVE_CSC_REG3			0x00108080
+#define SUNXI_TVE_COLOR_BURST_PAL_M		0x00000000
+#define SUNXI_TVE_CBR_LEVEL_PAL			0x00002828
+#define SUNXI_TVE_CBR_LEVEL_NTSC		0x0000004f
+#define SUNXI_TVE_BURST_PHASE_NTSC		0x00000000
+#define SUNXI_TVE_BURST_WIDTH_COMPOSITE		0x0016447e
+#define SUNXI_TVE_UNKNOWN2_PAL			0x0000e0e0
+#define SUNXI_TVE_UNKNOWN2_NTSC			0x0000a0a0
+#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC		0x001000f0
+#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE		0x000005a0
+#define SUNXI_TVE_CHROMA_BW_GAIN_COMP		0x00000002
+#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE		0x00000101
+#define SUNXI_TVE_RESYNC_NUM_PAL		0x800d000c
+#define SUNXI_TVE_RESYNC_NUM_NTSC		0x000e000c
+#define SUNXI_TVE_SLAVE_PARA_COMPOSITE		0x00000000
+
+void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode);
+void tvencoder_enable(struct sunxi_tve_reg * const tve);
+
+#endif /* _TVE_H */