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authorGabor Juhos <juhosg@openwrt.org>2013-06-13 10:59:35 (GMT)
committerTom Rini <trini@ti.com>2013-07-24 13:51:07 (GMT)
commitee8b1e29597bcf18bfebd6fd8eccc8e245046352 (patch)
tree0bc3e953a2bf45c34e985dd7a8714a674c3ce440 /arch
parentc325916563ac67ec5f86748060c2909a9b960bee (diff)
downloadu-boot-fsl-qoriq-ee8b1e29597bcf18bfebd6fd8eccc8e245046352.tar.xz
MIPS: mips32/cache.S: store cache line size in t8 register
Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/cpu/mips32/cache.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index fc13d3f..d3f156e 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -128,7 +128,7 @@ NESTED(mips_cache_reset, 0, ra)
move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
- li t4, CONFIG_SYS_CACHELINE_SIZE
+ li t8, CONFIG_SYS_CACHELINE_SIZE
li v0, MIPS_MAX_CACHE_SIZE
@@ -155,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra)
* Initialize the I-cache first,
*/
move a1, t2
- move a2, t4
+ move a2, t8
PTR_LA t7, mips_init_icache
jalr t7
@@ -163,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra)
* then initialize D-cache.
*/
move a1, t3
- move a2, t4
+ move a2, t8
PTR_LA t7, mips_init_dcache
jalr t7