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authorPaul Burton <paul.burton@imgtec.com>2016-09-21 10:18:59 (GMT)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-09-21 13:04:04 (GMT)
commit639200f6a0dcfe67e4c923b6108703e192946388 (patch)
tree2c086874eab5ecabfe7b0aac920d8608d5fbbc72 /board/BuR
parentd608254b0aa23607df1dcb5a7ca07de9a8ec9bb0 (diff)
downloadu-boot-fsl-qoriq-639200f6a0dcfe67e4c923b6108703e192946388.tar.xz
MIPS: Ensure cache ops complete in mips_cache_reset
Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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