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| author | Linus Walleij <linus.walleij@linaro.org> | 2011-10-02 11:52:52 (GMT) |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-10-21 22:42:04 (GMT) |
| commit | 96baa4c37695b4dac2bde981f59c38e7af19f2eb (patch) | |
| tree | 4c9c24511165b0571d8ac9579a982ba03483fd1e /board/altera | |
| parent | 349e83f071e2bf7bd9fec50377bbdcfb1a143666 (diff) | |
| download | u-boot-fsl-qoriq-96baa4c37695b4dac2bde981f59c38e7af19f2eb.tar.xz | |
serial: pl01x: drain PL01x FIFO before baudrate change
Not draining the FIFO and waiting for the UART to be non-busy
before changing baudrate results in crap characters on the
console, so let's wait for the FIFO to drain and the last
character to be clocked out before we do that.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'board/altera')
0 files changed, 0 insertions, 0 deletions