diff options
author | Wolfgang Denk <wd@atlas.denx.de> | 2006-03-06 22:18:48 (GMT) |
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committer | Wolfgang Denk <wd@atlas.denx.de> | 2006-03-06 22:18:48 (GMT) |
commit | 951a954b77ef30df1f5c1b7b9b4312e783b2cbb4 (patch) | |
tree | 8f94ab1a2e15fbf31c322e6be1f750e10ac2fe2f /board/delta | |
parent | ac7d97dcbb499c96c8182757f301dd2e09c9f49d (diff) | |
parent | bfc81252c0de3bfcf92c7c35bc04341fb33e4e4e (diff) | |
download | u-boot-fsl-qoriq-951a954b77ef30df1f5c1b7b9b4312e783b2cbb4.tar.xz |
Merge with /home/wd/git/u-boot/master
Code cleanup.
Diffstat (limited to 'board/delta')
-rw-r--r-- | board/delta/config.mk | 1 | ||||
-rw-r--r-- | board/delta/lowlevel_init.S | 230 | ||||
-rw-r--r-- | board/delta/nand.c | 54 |
3 files changed, 141 insertions, 144 deletions
diff --git a/board/delta/config.mk b/board/delta/config.mk index b269b6e..9564625 100644 --- a/board/delta/config.mk +++ b/board/delta/config.mk @@ -6,4 +6,3 @@ TEXT_BASE = 0xa3008000 # Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE) BOARDLIBS = drivers/nand/libnand.a - diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S index 66e7575..498cf7f 100644 --- a/board/delta/lowlevel_init.S +++ b/board/delta/lowlevel_init.S @@ -16,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -32,33 +32,33 @@ DRAM_SIZE: .long CFG_DRAM_SIZE /* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm +.macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 +.endm .macro wait time - ldr r2, =OSCR - mov r3, #0 - str r3, [r2] + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] 0: - ldr r3, [r2] - cmp r3, \time - bls 0b + ldr r3, [r2] + cmp r3, \time + bls 0b .endm /* - * Memory setup + * Memory setup */ .globl lowlevel_init lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ - mov r10, lr - - /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ + mov r10, lr + + /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ ldr r0, =GPIO97 ldr r1, =0x801 str r1, [r0] @@ -66,24 +66,24 @@ lowlevel_init: ldr r0, =GPIO98 ldr r1, =0x801 str r1, [r0] - - /* tebrandt - ASCR, clear the RDH bit */ - ldr r0, =ASCR - ldr r1, [r0] - bic r1, r1, #0x80000000 - str r1, [r0] - + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + /* ---------------------------------------------------------------- */ - /* Enable memory interface */ + /* Enable memory interface */ /* ---------------------------------------------------------------- */ /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ /* ---------------------------------------------------------------- */ -; wait #300 - +; wait #300 + mem_init: #define NEW_SDRAM_INIT 1 @@ -99,11 +99,11 @@ mem_init: /* 2. Programm MDCNFG, leaving DMCEN de-asserted */ ldr r0, =MDCNFG ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13) - /* ldr r1, =0x80000403 */ + /* ldr r1, =0x80000403 */ str r1, [r0] ldr r1, [r0] /* delay until written */ - /* 3. wait nop power up waiting period (200ms) + /* 3. wait nop power up waiting period (200ms) * optimization: Steps 4+6 can be done during this */ wait #300 @@ -127,7 +127,7 @@ mem_init: ldr r1, =0x60000033 str r1, [r0] wait #300 - + /* Configure MDREFR */ ldr r0, =MDREFR ldr r1, =0x00000006 @@ -142,48 +142,48 @@ mem_init: #else /* NEW_SDRAM_INIT */ - + /* configure the MEMCLKCFG register */ - ldr r1, =MEMCLKCFG - ldr r2, =0x00010001 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =MEMCLKCFG + ldr r2, =0x00010001 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[0] to data flash SRAM mode */ - ldr r1, =CSADRCFG0 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG0 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[1] to data flash SRAM mode */ - ldr r1, =CSADRCFG1 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG1 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set MSC 0 register for SRAM memory */ - ldr r1, =MSC0 - ldr r2, =0x11191119 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =MSC0 + ldr r2, =0x11191119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[2] to data flash SRAM mode */ - ldr r1, =CSADRCFG2 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG2 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[3] to VLIO mode */ - ldr r1, =CSADRCFG3 - ldr r2, =0x0032080B - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN + ldr r1, =CSADRCFG3 + ldr r2, =0x0032080B + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN /* set MSC 1 register for VLIO memory */ - ldr r1, =MSC1 - ldr r2, =0x123C1119 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN + ldr r1, =MSC1 + ldr r2, =0x123C1119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN #if 0 /* This does not work in Zylonite. -SC */ @@ -240,11 +240,11 @@ mem_init: ldr r2, [r1] /* Hardware DDR Read-Strobe Delay Calibration */ - ldr r0, =DDR_HCAL @ DDR_HCAL - ldr r1, =0x803ffc07 @ the offset is correct? -SC - str r1, [r0] + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] wait #5 - ldr r1, [r0] + ldr r1, [r0] /* Here we assume the hardware calibration alwasy be successful. -SC */ /* Set DMCEN bit in MDCNFG Register */ @@ -254,20 +254,20 @@ mem_init: str r1, [r0] #endif /* NEW_SDRAM_INIT */ - + #ifndef CFG_SKIP_DRAM_SCRUB /* scrub/init SDRAM if enabled/present */ ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */ mov r0, #0 /* scrub with 0x0000:0000 */ mov r1, #0 - mov r2, #0 + mov r2, #0 mov r3, #0 - mov r4, #0 + mov r4, #0 mov r5, #0 - mov r6, #0 + mov r6, #0 mov r7, #0 -10: /* fastScrubLoop */ +10: /* fastScrubLoop */ subs r9, r9, #32 /* 8 words/line */ stmia r8!, {r0-r7} beq 15f @@ -281,25 +281,25 @@ mem_init: /* Disable software and data breakpoints */ mov r0, #0 - mcr p15,0,r0,c14,c8,0 // ibcr0 - mcr p15,0,r0,c14,c9,0 // ibcr1 - mcr p15,0,r0,c14,c4,0 // dbcon + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ /* Enable all debug functionality */ mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 // dcsr + mcr p14,0,r0,c10,c0,0 /* dcsr */ endlowlevel_init: - mov pc, lr + mov pc, lr /* @******************************************************************************** @ DDR calibration -@ +@ @ This function is used to calibrate DQS delay lines. -@ Monahans supports three ways to do it. One is software +@ Monahans supports three ways to do it. One is software @ calibration. Two is hardware calibration. Three is hybrid @ calibration. @ @@ -308,15 +308,15 @@ endlowlevel_init: ddr_calibration: @ Case 1: Write the correct delay value once - @ Configure DDR_SCAL Register - ldr r0, =DDR_SCAL @ DDR_SCAL -q ldr r1, =0xaf2f2f2f - str r1, [r0] - ldr r1, [r0] + @ Configure DDR_SCAL Register + ldr r0, =DDR_SCAL @ DDR_SCAL +q ldr r1, =0xaf2f2f2f + str r1, [r0] + ldr r1, [r0] */ /* @ Case 2: Software Calibration @ Write test pattern to memory - ldr r5, =0x0faf0faf @ Data Pattern + ldr r5, =0x0faf0faf @ Data Pattern ldr r4, =0xa0000000 @ DDR ram str r5, [r4] @@ -328,11 +328,11 @@ ddr_loop1: cmp r1, =0xf ble end_loop mov r3, r1 - mov r0, r1, lsl #30 + mov r0, r1, lsl #30 orr r3, r3, r0 - mov r0, r1, lsl #22 + mov r0, r1, lsl #22 orr r3, r3, r0 - mov r0, r1, lsl #14 + mov r0, r1, lsl #14 orr r3, r3, r0 orr r3, r3, =0x80000000 ldr r2, =DDR_SCAL @@ -346,16 +346,16 @@ ddr_loop2: add r1, r1, =0x1 cmp r1, =0xf ble end_loop - mov r3, r1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - str r3, [r2] + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] ldr r2, [r4] cmp r2, r5 @@ -364,22 +364,22 @@ ddr_loop2: add r3, r6, r7 lsr r3, r3, =0x1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + end_loop: @ Case 3: Hardware Calibratoin - ldr r0, =DDR_HCAL @ DDR_HCAL - ldr r1, =0x803ffc07 @ the offset is correct? -SC - str r1, [r0] + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] wait #5 - ldr r1, [r0] - mov pc, lr + ldr r1, [r0] + mov pc, lr */ diff --git a/board/delta/nand.c b/board/delta/nand.c index 5876727..50def59 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -95,7 +95,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) unsigned long rest = len & 0x3; unsigned long *long_buf; int i; - + DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); if(bytes_multi) { for(i=0; i<bytes_multi; i+=4) { @@ -110,7 +110,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) } -/* +/* * These functions are quite problematic for the DFC. Luckily they are * not used in the current nand code, except for nand_command, which * we've defined our own anyway. The problem is, that we always need @@ -152,7 +152,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) *long_buf = NDDB; } } - + /* ...then the rest */ if(rest) { unsigned long rest_data = NDDB; @@ -176,7 +176,7 @@ static u16 dfc_read_word(struct mtd_info *mtd) static unsigned long read_buf = 0; static int bytes_read = -1; -/* +/* * read a byte from NDDB Because we can only read 4 bytes from NDDB at * a time, we buffer the remaining bytes. The buffer is reset when a * new command is sent to the chip. @@ -196,7 +196,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd) if(bytes_read < 0) { read_buf = NDDB; - dummy = NDDB; + dummy = NDDB; bytes_read = 0; } byte = (unsigned char) (read_buf>>(8 * bytes_read++)); @@ -211,7 +211,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd) static unsigned long get_delta(unsigned long start) { unsigned long cur = OSCR; - + if(cur < start) /* OSCR overflowed */ return (cur + (start^0xffffffff)); else @@ -239,14 +239,14 @@ static void dfc_clear_nddb() static unsigned long dfc_wait_event(unsigned long event) { unsigned long ndsr, timeout, start = OSCR; - + if(!event) return 0xff000000; else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; else timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; - + while(1) { ndsr = NDSR; if(ndsr & event) { @@ -257,7 +257,7 @@ static unsigned long dfc_wait_event(unsigned long event) DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); return 0xff000000; } - + } return ndsr; } @@ -271,13 +271,13 @@ static void dfc_new_cmd() while(retry++ <= CFG_NAND_SENDCMD_RETRY) { /* Clear NDSR */ NDSR = 0xFFF; - + /* set NDCR[NDRUN] */ if(!(NDCR & NDCR_ND_RUN)) NDCR |= NDCR_ND_RUN; - + status = dfc_wait_event(NDSR_WRCMDREQ); - + if(status & NDSR_WRCMDREQ) return; @@ -303,7 +303,7 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) } else if(state == FL_ERASING) { event = NDSR_CS0_CMDD | NDSR_CS0_BBD; } - + ndsr = dfc_wait_event(event); if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) @@ -312,7 +312,7 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) } /* cmdfunc send commands to the DFC */ -static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, +static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column, int page_addr) { /* register struct nand_chip *this = mtd->priv; */ @@ -404,7 +404,7 @@ static void dfc_gpio_init() /* no idea what is done here, see zylonite.c */ GPIO4 = 0x1; - + DF_ALE_WE1 = 0x00000001; DF_ALE_WE2 = 0x00000001; DF_nCS0 = 0x00000001; @@ -464,10 +464,10 @@ void board_nand_init(struct nand_chip *nand) CKENA |= (CKENA_4_NAND | CKENA_9_SMC); #undef CFG_TIMING_TIGHT -#ifndef CFG_TIMING_TIGHT - tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), +#ifndef CFG_TIMING_TIGHT + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), DFC_MAX_tCH); - tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), DFC_MAX_tCS); tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), DFC_MAX_tWH); @@ -485,9 +485,9 @@ void board_nand_init(struct nand_chip *nand) DFC_MAX_tAR); #else /* this is the tight timing */ - tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), DFC_MAX_tCH); - tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), DFC_MAX_tCS); tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), DFC_MAX_tWH); @@ -523,13 +523,11 @@ void board_nand_init(struct nand_chip *nand) (tRP_high << 6) | (tRH << 3) | (tRP << 0); - + NDTR1CS0 = (tR << 16) | (tWHR << 4) | (tAR << 0); - - /* If it doesn't work (unlikely) think about: * - ecc enable * - chip select don't care @@ -544,7 +542,7 @@ void board_nand_init(struct nand_chip *nand) * - ND_RDY : clears command buffer */ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ - + NDCR = (NDCR_SPARE_EN | /* use the spare area */ NDCR_DWIDTH_C | /* 16bit DFC data bus width */ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ @@ -557,17 +555,17 @@ void board_nand_init(struct nand_chip *nand) NDCR_CS1_CMDDM | NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ NDCR_CS1_BBDM | - NDCR_DBERRM | /* double bit error ir masked */ + NDCR_DBERRM | /* double bit error ir masked */ NDCR_SBERRM | /* single bit error ir masked */ NDCR_WRDREQM | /* write data request ir masked */ NDCR_RDDREQM | /* read data request ir masked */ NDCR_WRCMDREQM); /* write command request ir masked */ - + /* wait 10 us due to cmd buffer clear reset */ /* wait(10); */ - - + + nand->hwcontrol = dfc_hwcontrol; /* nand->dev_ready = dfc_device_ready; */ nand->eccmode = NAND_ECC_SOFT; |