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authorMatthias Fuchs <matthias.fuchs@esd-electronics.com>2008-10-28 12:36:56 (GMT)
committerStefan Roese <sr@denx.de>2008-10-31 09:37:50 (GMT)
commit492aa9ea13791ca4591b5bde895a425e27ae2d10 (patch)
tree81a41e8c968861ad9252c734f08166edb9b61752 /board/esd/pmc440/pmc440.h
parent295133258a44f97a57fb2ec339aecfda11f4db95 (diff)
downloadu-boot-fsl-qoriq-492aa9ea13791ca4591b5bde895a425e27ae2d10.tar.xz
ppc4xx: Clean up PMC440 header
-Codingstyle cleanup -Remove unused GPIO define Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/pmc440/pmc440.h')
-rw-r--r--board/esd/pmc440/pmc440.h17
1 files changed, 7 insertions, 10 deletions
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
index d834f25..295cec1 100644
--- a/board/esd/pmc440/pmc440.h
+++ b/board/esd/pmc440/pmc440.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
*
* See file CREDITS for list of people who contributed to this
@@ -24,8 +24,7 @@
#ifndef __PMC440_H__
#define __PMC440_H__
-
-/*-----------------------------------------------------------------------
+/*
* GPIOs
*/
#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
@@ -41,9 +40,10 @@
#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
-#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */
-/* FPGA programming pin configuration */
+/*
+ * FPGA programming pin configuration
+ */
#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
@@ -51,7 +51,7 @@
#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
-/*-----------------------------------------------------------------------
+/*
* FPGA interface
*/
#define FPGA_BA CONFIG_SYS_FPGA_BASE0
@@ -103,7 +103,6 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
#define RESET_OUT (1 << 19)
#define IRIGB_R_OUT (1 << 14)
-
/* status register */
#define STATUS_VERSION_SHIFT 24
#define STATUS_VERSION_MASK 0xff000000
@@ -115,13 +114,11 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
#define STATUS_FIFO_ISF (1 << 9)
#define STATUS_HOST_ISF (1 << 8)
-
/* inputs */
#define RESET_IN (1 << 0)
#define CLOCK_IN (1 << 1)
#define IRIGB_R_IN (1 << 5)
-
/* hostctrl register */
#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
@@ -137,7 +134,7 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000)
#define NGCC_CTRL_FPGARST_N (1 << 2)
-/*-----------------------------------------------------------------------
+/*
* FPGA to PPC interrupt
*/
#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */