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| author | Yung-Ching LIN <yungching0725@gmail.com> | 2017-02-21 01:56:56 (GMT) |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2017-03-26 14:58:11 (GMT) |
| commit | ec7aa8fd677f52a6175265aeb7b7f0345d9850c2 (patch) | |
| tree | 42fd9a9744f791770d6c518394907239699e7ac9 /board/espt/MAINTAINERS | |
| parent | d42db168e68c6d7b87da673321ac25c657fb4a3a (diff) | |
| download | u-boot-fsl-qoriq-ec7aa8fd677f52a6175265aeb7b7f0345d9850c2.tar.xz | |
board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>
Diffstat (limited to 'board/espt/MAINTAINERS')
0 files changed, 0 insertions, 0 deletions