diff options
author | wdenk <wdenk> | 2002-11-03 00:24:07 (GMT) |
---|---|---|
committer | wdenk <wdenk> | 2002-11-03 00:24:07 (GMT) |
commit | c609719b8d1b2dca590e0ed499016d041203e403 (patch) | |
tree | 7ea1755d80903ff972f312a249eb856061d40e15 /board/evb64260 | |
parent | 5b1d713721c3ea02549940133f09236783dda1f9 (diff) | |
download | u-boot-fsl-qoriq-c609719b8d1b2dca590e0ed499016d041203e403.tar.xz |
Initial revision
Diffstat (limited to 'board/evb64260')
-rw-r--r-- | board/evb64260/eth_addrtbl.c | 225 | ||||
-rw-r--r-- | board/evb64260/pci.c | 691 | ||||
-rw-r--r-- | board/evb64260/sdram_init.c | 629 | ||||
-rw-r--r-- | board/evb64260/serial.c | 191 |
4 files changed, 1736 insertions, 0 deletions
diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c new file mode 100644 index 0000000..ea4925a --- /dev/null +++ b/board/evb64260/eth_addrtbl.c @@ -0,0 +1,225 @@ +#include <common.h> +#include <malloc.h> +#include <galileo/gt64260R.h> +#include <galileo/core.h> +#include <asm/cache.h> +#include "eth.h" +#include "eth_addrtbl.h" + +#define TRUE 1 +#define FALSE 0 + +#define PRINTF printf + +#ifdef CONFIG_GT_USE_MAC_HASH_TABLE + +static u32 addressTableHashMode[ GAL_ETH_DEVS ] = { 0, }; +static u32 addressTableHashSize[ GAL_ETH_DEVS ] = { 0, }; +static addrTblEntry *addressTableBase[ GAL_ETH_DEVS ] = { 0, }; +static void *realAddrTableBase[ GAL_ETH_DEVS ] = { 0, }; + +static const u32 hashLength[ 2 ] = { + (0x8000), /* 8K * 4 entries */ + (0x8000/16), /* 512 * 4 entries */ +}; + +/* Initialize the address table for a port, if needed */ +unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector) +{ + unsigned int tableBase; + + if( port < 0 || port >= GAL_ETH_DEVS ) { + printf("%s: Invalid port number %d\n", __FUNCTION__, port ); + return 0; + } + + if (hashMode > 1) { + printf("%s: Invalid Hash Mode %d\n", __FUNCTION__, port ); + return 0; + } + + if ( realAddrTableBase[port] && + ( addressTableHashSize[port] != hashSizeSelector )) { + /* we have been here before, + * but now we want a different sized table + */ + free( realAddrTableBase[port] ); + realAddrTableBase[port] = 0; + addressTableBase[port] = 0; + + } + + tableBase = (unsigned int)addressTableBase[port]; + /* we get called for every probe, so only do this once */ + if ( !tableBase ) { + int bytes = hashLength[hashSizeSelector] * sizeof(addrTblEntry); + + tableBase = (unsigned int)realAddrTableBase[port] = malloc(bytes+64); + + if(!tableBase) + { + printf("%s: alloc memory failed \n", __FUNCTION__); + return 0; + } + + /* align to octal byte */ + if(tableBase&63) tableBase=(tableBase+63) & ~63; + + addressTableHashMode[port] = hashMode; + addressTableHashSize[port] = hashSizeSelector; + addressTableBase[port] = (addrTblEntry *)tableBase; + + memset((void *)tableBase,0,bytes); + } + + return tableBase; +} + +/* + * ---------------------------------------------------------------------------- + * This function will calculate the hash function of the address. + * depends on the hash mode and hash size. + * Inputs + * macH - the 2 most significant bytes of the MAC address. + * macL - the 4 least significant bytes of the MAC address. + * hashMode - hash mode 0 or hash mode 1. + * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800) + * Outputs + * return the calculated entry. + */ +u32 +hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode) +{ + u32 hashResult; + u32 addrH; + u32 addrL; + u32 addr0; + u32 addr1; + u32 addr2; + u32 addr3; + u32 addrHSwapped; + u32 addrLSwapped; + + + addrH = NIBBLE_SWAPPING_16_BIT( macH ); + addrL = NIBBLE_SWAPPING_32_BIT( macL ); + + addrHSwapped = FLIP_4_BITS( addrH & 0xf ) + + ((FLIP_4_BITS( (addrH >> 4) & 0xf)) << 4) + + ((FLIP_4_BITS( (addrH >> 8) & 0xf)) << 8) + + ((FLIP_4_BITS( (addrH >> 12) & 0xf)) << 12); + + addrLSwapped = FLIP_4_BITS( addrL & 0xf ) + + ((FLIP_4_BITS( (addrL >> 4) & 0xf)) << 4) + + ((FLIP_4_BITS( (addrL >> 8) & 0xf)) << 8) + + ((FLIP_4_BITS( (addrL >> 12) & 0xf)) << 12) + + ((FLIP_4_BITS( (addrL >> 16) & 0xf)) << 16) + + ((FLIP_4_BITS( (addrL >> 20) & 0xf)) << 20) + + ((FLIP_4_BITS( (addrL >> 24) & 0xf)) << 24) + + ((FLIP_4_BITS( (addrL >> 28) & 0xf)) << 28); + + addrH = addrHSwapped; + addrL = addrLSwapped; + + if( hash_mode == 0 ) { + addr0 = (addrL >> 2) & 0x03f; + addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2; + addr2 = (addrL >> 15) & 0x1ff; + addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8); + } else { + addr0 = FLIP_6_BITS( addrL & 0x03f ); + addr1 = FLIP_9_BITS( ((addrL >> 6) & 0x1ff)); + addr2 = FLIP_9_BITS( (addrL >> 15) & 0x1ff); + addr3 = FLIP_9_BITS( (((addrL >> 24) & 0x0ff) | ((addrH & 0x1) << 8))); + } + + hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); + + if( HashSize == _8K_TABLE ) { + hashResult = hashResult & 0xffff; + } else { + hashResult = hashResult & 0x07ff; + } + + return( hashResult ); +} + + +/* + * ---------------------------------------------------------------------------- + * This function will add an entry to the address table. + * depends on the hash mode and hash size that was initialized. + * Inputs + * port - ETHERNET port number. + * macH - the 2 most significant bytes of the MAC address. + * macL - the 4 least significant bytes of the MAC address. + * skip - if 1, skip this address. + * rd - the RD field in the address table. + * Outputs + * address table entry is added. + * TRUE if success. + * FALSE if table full + */ +int +addAddressTableEntry( + u32 port, + u32 macH, + u32 macL, + u32 rd, + u32 skip ) +{ + addrTblEntry *entry; + u32 newHi; + u32 newLo; + u32 i; + + newLo = (((macH >> 4) & 0xf) << 15) + | (((macH >> 0) & 0xf) << 11) + | (((macH >> 12) & 0xf) << 7) + | (((macH >> 8) & 0xf) << 3) + | (((macL >> 20) & 0x1) << 31) + | (((macL >> 16) & 0xf) << 27) + | (((macL >> 28) & 0xf) << 23) + | (((macL >> 24) & 0xf) << 19) + | (skip << SKIP_BIT) | (rd << 2) | VALID; + + newHi = (((macL >> 4) & 0xf) << 15) + | (((macL >> 0) & 0xf) << 11) + | (((macL >> 12) & 0xf) << 7) + | (((macL >> 8) & 0xf) << 3) + | (((macL >> 21) & 0x7) << 0); + + /* + * Pick the appropriate table, start scanning for free/reusable + * entries at the index obtained by hashing the specified MAC address + */ + entry = addressTableBase[port]; + entry += hashTableFunction( macH, macL, addressTableHashSize[port], + addressTableHashMode[port] ); + for( i = 0; i < HOP_NUMBER; i++, entry++ ) { + if( !(entry->lo & VALID) /*|| (entry->lo & SKIP)*/ ) { + break; + } else { /* if same address put in same position */ + if( ((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8)) + && (entry->hi == newHi) ) + { + break; + } + } + } + + if( i == HOP_NUMBER ) { + PRINTF( "addGT64260addressTableEntry: table section is full\n" ); + return( FALSE ); + } + + /* + * Update the selected entry + */ + entry->hi = newHi; + entry->lo = newLo; + DCACHE_FLUSH_N_SYNC( (u32)entry, MAC_ENTRY_SIZE ); + return( TRUE ); +} + +#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */ diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c new file mode 100644 index 0000000..8e9178d --- /dev/null +++ b/board/evb64260/pci.c @@ -0,0 +1,691 @@ +/* PCI.c - PCI functions */ + +/* Copyright - Galileo technology. */ + +#include <common.h> +#include <pci.h> + +#include <galileo/pci.h> + +static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { +#ifdef CONFIG_ZUMA_V2 + {0,0,0,0,0,0,0,29, [8 ... PCI_MAX_DEVICES-1]=0}, + {0,0,0,0,0,0,0,28, [8 ... PCI_MAX_DEVICES-1]=0} +#else /* EVB??? This is a guess */ + {0,0,0,0,0,0,0,27,27, [9 ... PCI_MAX_DEVICES-1]=0}, + {0,0,0,0,0,0,0,29,29, [9 ... PCI_MAX_DEVICES-1]=0} +#endif +}; + +static const unsigned int pci_p2p_configuration_reg[]={ + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION}; + +static const unsigned int pci_configuration_address[]={ + PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS}; + +static const unsigned int pci_configuration_data[]={ + PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, + PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER}; + +static const unsigned int pci_error_cause_reg[]={ + PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE}; + +static const unsigned int pci_arbiter_control[]={ + PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL}; + +static const unsigned int pci_snoop_control_base_0_low[]={ + PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW}; +static const unsigned int pci_snoop_control_top_0[]={ + PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0}; + +static const unsigned int pci_access_control_base_0_low[]={ + PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW}; +static const unsigned int pci_access_control_top_0[]={ + PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0}; + +static const unsigned int pci_scs_bank_size[2][4] = { + {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, + PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, + {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, + PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}}; + +static const unsigned int pci_p2p_configuration[] = { + PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION}; + +/******************************************************************** +* pciWriteConfigReg - Write to a PCI configuration register +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* +* +* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,unsigned int pciDevNum,unsigned int data) +{ + volatile unsigned int DataForAddrReg; + unsigned int functionNum; + unsigned int busNum = 0; + unsigned int addr; + + if(pciDevNum > 32) /* illegal device Number */ + return; + if(pciDevNum == SELF) /* configure our configuration space. */ + { + pciDevNum = (GTREGREAD(pci_p2p_configuration_reg[host]) >> 24) & 0x1f; + busNum = GTREGREAD(pci_p2p_configuration_reg[host]) & 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = ( regOffset | pciDevNum | functionNum | busNum) | BIT31; + GT_REG_WRITE(pci_configuration_address[host],DataForAddrReg); + GT_REG_READ(pci_configuration_address[host], &addr); + if (addr != DataForAddrReg) return; + GT_REG_WRITE(pci_configuration_data[host],data); +} + +/******************************************************************** +* pciReadConfigReg - Read from a PCI0 configuration register +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec) +* pciDevNum: The device number needs to be addressed. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|00| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,unsigned int pciDevNum) +{ + volatile unsigned int DataForAddrReg; + unsigned int data; + unsigned int functionNum; + unsigned int busNum = 0; + + if(pciDevNum > 32) /* illegal device Number */ + return 0xffffffff; + if(pciDevNum == SELF) /* configure our configuration space. */ + { + pciDevNum = (GTREGREAD(pci_p2p_configuration_reg[host]) >> 24) & 0x1f; + busNum = GTREGREAD(pci_p2p_configuration_reg[host]) & 0xff0000; + } + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xfc; + DataForAddrReg = (regOffset | pciDevNum | functionNum | busNum) | BIT31 ; + GT_REG_WRITE(pci_configuration_address[host],DataForAddrReg); + GT_REG_READ(pci_configuration_address[host], &data); + if (data != DataForAddrReg) + return 0xffffffff; + GT_REG_READ(pci_configuration_data[host], &data); + return data; +} + +/******************************************************************** +* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. +* +* Inputs: unsigned int regOffset - The register offset as it apears in the +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +* The configuration Address is configure as type-I (bits[1:0] = '01') due to +* PCI spec referring to P2P. +* +*********************************************************************/ +void pciOverBridgeWriteConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum,unsigned int data) +{ + unsigned int DataForReg; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if(pciDevNum == SELF) /* This board */ + { + DataForReg = ( regOffset | pciDevNum | functionNum) | BIT0; + } + else + { + DataForReg = ( regOffset | pciDevNum | functionNum | busNum) | + BIT31 | BIT0; + } + GT_REG_WRITE(pci_configuration_address[host],DataForReg); + if(pciDevNum == SELF) /* This board */ + { + GT_REG_WRITE(pci_configuration_data[host],data); + } + else /* configuration Transaction over the pci. */ + { + /* The PCI is working in LE Mode So it swap the Data. */ + GT_REG_WRITE(pci_configuration_data[host],WORD_SWAP(data)); + } +} + + +/******************************************************************** +* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. +* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. +* RETURNS: data , if the data == 0xffffffff check the master abort bit in the +* cause register to make sure the data is valid +* +* Configuration Address 0xCF8: +* +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* |congif|Reserved| Bus |Device|Function|Register|01| +* |Enable| |Number|Number| Number | Number | | <=field Name +* +*********************************************************************/ +unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, + unsigned int regOffset, + unsigned int pciDevNum, + unsigned int busNum) +{ + unsigned int DataForReg; + unsigned int data; + unsigned int functionNum; + + functionNum = regOffset & 0x00000700; + pciDevNum = pciDevNum << 11; + regOffset = regOffset & 0xff; + busNum = busNum << 16; + if (pciDevNum == SELF) /* This board */ + { + DataForReg = (regOffset | pciDevNum | functionNum) | BIT31 ; + } + else /* agent on another bus */ + { + DataForReg = (regOffset | pciDevNum | functionNum | busNum) | + BIT0 | BIT31 ; + } + GT_REG_WRITE(pci_configuration_address[host],DataForReg); + if (pciDevNum == SELF) /* This board */ + { + GT_REG_READ(pci_configuration_data[host], &data); + return data; + } + else /* The PCI is working in LE Mode So it swap the Data. */ + { + GT_REG_READ(pci_configuration_data[host], &data); + return WORD_SWAP(data); + } +} + +/******************************************************************** +* pciGetRegOffset - Gets the register offset for this region config. +* +* INPUT: Bus, Region - The bus and region we ask for its base address. +* OUTPUT: N/A +* RETURNS: PCI register base address +*********************************************************************/ +static unsigned int pciGetRegOffset(PCI_HOST host, PCI_REGION region) +{ + switch (host) + { + case PCI_HOST0: + switch(region) { + case PCI_IO: return PCI_0I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: return PCI_0MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: return PCI_0MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: return PCI_0MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: return PCI_0MEMORY3_LOW_DECODE_ADDRESS; + } + case PCI_HOST1: + switch(region) { + case PCI_IO: return PCI_1I_O_LOW_DECODE_ADDRESS; + case PCI_REGION0: return PCI_1MEMORY0_LOW_DECODE_ADDRESS; + case PCI_REGION1: return PCI_1MEMORY1_LOW_DECODE_ADDRESS; + case PCI_REGION2: return PCI_1MEMORY2_LOW_DECODE_ADDRESS; + case PCI_REGION3: return PCI_1MEMORY3_LOW_DECODE_ADDRESS; + } + } + return PCI_0MEMORY0_LOW_DECODE_ADDRESS; +} + +static unsigned int pciGetRemapOffset(PCI_HOST host, PCI_REGION region) +{ + switch (host) + { + case PCI_HOST0: + switch(region) { + case PCI_IO: return PCI_0I_O_ADDRESS_REMAP; + case PCI_REGION0: return PCI_0MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: return PCI_0MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: return PCI_0MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: return PCI_0MEMORY3_ADDRESS_REMAP; + } + case PCI_HOST1: + switch(region) { + case PCI_IO: return PCI_1I_O_ADDRESS_REMAP; + case PCI_REGION0: return PCI_1MEMORY0_ADDRESS_REMAP; + case PCI_REGION1: return PCI_1MEMORY1_ADDRESS_REMAP; + case PCI_REGION2: return PCI_1MEMORY2_ADDRESS_REMAP; + case PCI_REGION3: return PCI_1MEMORY3_ADDRESS_REMAP; + } + } + return PCI_0MEMORY0_ADDRESS_REMAP; +} + +bool pciMapSpace(PCI_HOST host, PCI_REGION region, unsigned int remapBase, unsigned int bankBase,unsigned int bankLength) +{ + unsigned int low=0xfff; + unsigned int high=0x0; + unsigned int regOffset=pciGetRegOffset(host, region); + unsigned int remapOffset=pciGetRemapOffset(host, region); + + if(bankLength!=0) { + low = (bankBase >> 20) & 0xfff; + high=((bankBase+bankLength)>>20)-1; + } + + GT_REG_WRITE(regOffset, low | (1<<24)); /* no swapping */ + GT_REG_WRITE(regOffset+8, high); + + if(bankLength!=0) { /* must do AFTER writing maps */ + GT_REG_WRITE(remapOffset, remapBase>>20); /* sorry, 32 bits only. + dont support upper 32 + in this driver */ + } + return true; +} + +unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region) +{ + unsigned int low; + unsigned int regOffset=pciGetRegOffset(host, region); + GT_REG_READ(regOffset,&low); + return (low&0xfff)<<20; +} + +unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region) +{ + unsigned int low,high; + unsigned int regOffset=pciGetRegOffset(host, region); + GT_REG_READ(regOffset,&low); + GT_REG_READ(regOffset+8,&high); + high&=0xfff; + low&=0xfff; + if(high<=low) return 0; + return (high+1-low)<<20; +} + +/******************************************************************** +* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. +* +* Inputs: base and size of PCI SCS +*********************************************************************/ +void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, unsigned int pciDramBase,unsigned int pciDramSize) +{ + pciDramBase = pciDramBase & 0xfffff000; + pciDramBase = pciDramBase | (pciReadConfigReg(host, + PCI_SCS_0_BASE_ADDRESS + 4*bank,SELF) & 0x00000fff); + pciWriteConfigReg(host,PCI_SCS_0_BASE_ADDRESS + 4*bank,SELF,pciDramBase); + if(pciDramSize == 0) + pciDramSize ++; + GT_REG_WRITE(pci_scs_bank_size[host][bank], pciDramSize-1); +} + + +/******************************************************************** +* pciSetRegionFeatures - This function modifys one of the 8 regions with +* feature bits given as an input. +* - Be advised to check the spec before modifying them. +* Inputs: PCI_PROTECT_REGION region - one of the eight regions. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. +* Returns: false if one of the parameters is erroneous true otherwise. +*********************************************************************/ +bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,unsigned int features, + unsigned int baseAddress,unsigned int regionLength) +{ + unsigned int accessLow; + unsigned int accessHigh; + unsigned int accessTop = baseAddress + regionLength; + + if(regionLength == 0) /* close the region. */ + { + pciDisableAccessRegion(host, region); + return true; + } + /* base Address is store is bits [11:0] */ + accessLow = (baseAddress & 0xfff00000) >> 20; + /* All the features are update according to the defines in pci.h (to be on + the safe side we disable bits: [11:0] */ + accessLow = accessLow | (features & 0xfffff000); + /* write to the Low Access Region register */ + GT_REG_WRITE( pci_access_control_base_0_low[host] + 0x10*region,accessLow); + + accessHigh = (accessTop & 0xfff00000) >> 20; + + /* write to the High Access Region register */ + GT_REG_WRITE(pci_access_control_top_0[host] + 0x10*region,accessHigh - 1); + return true; +} + +/******************************************************************** +* pciDisableAccessRegion - Disable The given Region by writing MAX size +* to its low Address and MIN size to its high Address. +* +* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. +* Returns: N/A. +*********************************************************************/ +void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region) +{ + /* writing back the registers default values. */ + GT_REG_WRITE(pci_access_control_base_0_low[host] + 0x10*region,0x01001fff); + GT_REG_WRITE(pci_access_control_top_0[host] + 0x10*region,0); +} + +/******************************************************************** +* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true. +*********************************************************************/ +bool pciArbiterEnable(PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ(pci_arbiter_control[host],®Data); + GT_REG_WRITE(pci_arbiter_control[host],regData | BIT31); + return true; +} + +/******************************************************************** +* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. +* +* Inputs: N/A +* Returns: true +*********************************************************************/ +bool pciArbiterDisable(PCI_HOST host) +{ + unsigned int regData; + + GT_REG_READ(pci_arbiter_control[host],®Data); + GT_REG_WRITE(pci_arbiter_control[host],regData & 0x7fffffff); + return true; +} + +/******************************************************************** +* pciParkingDisable - Park on last option disable, with this function you can +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. +* +* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* Returns: true +*********************************************************************/ +bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, + PCI_AGENT_PARK externalAgent0, + PCI_AGENT_PARK externalAgent1, + PCI_AGENT_PARK externalAgent2, + PCI_AGENT_PARK externalAgent3, + PCI_AGENT_PARK externalAgent4, + PCI_AGENT_PARK externalAgent5) +{ + unsigned int regData; + unsigned int writeData; + + GT_REG_READ(pci_arbiter_control[host],®Data); + writeData = (internalAgent << 14) + (externalAgent0 << 15) + \ + (externalAgent1 << 16) + (externalAgent2 << 17) + \ + (externalAgent3 << 18) + (externalAgent4 << 19) + \ + (externalAgent5 << 20); + regData = (regData & ~(0x7f<<14)) | writeData; + GT_REG_WRITE(pci_arbiter_control[host],regData); + return true; +} + +/******************************************************************** +* pciSetRegionSnoopMode - This function modifys one of the 4 regions which +* supports Cache Coherency in the PCI_n interface. +* Inputs: region - One of the four regions. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. +* Returns: false if one of the parameters is wrong otherwise return true. +*********************************************************************/ +bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength) +{ + unsigned int snoopXbaseAddress; + unsigned int snoopXtopAddress; + unsigned int data; + unsigned int snoopHigh = baseAddress + regionLength; + + if( (region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB) ) + return false; + snoopXbaseAddress = pci_snoop_control_base_0_low[host] + 0x10 * region; + snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; + if(regionLength == 0) /* closing the region */ + { + GT_REG_WRITE(snoopXbaseAddress,0x0000ffff); + GT_REG_WRITE(snoopXtopAddress,0); + return true; + } + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + data = (baseAddress >> 20) | snoopType << 12; + GT_REG_WRITE(snoopXbaseAddress,data); + snoopHigh = (snoopHigh & 0xfff00000) >> 20; + GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1); + return true; +} + +/* + * + */ + +static int gt_read_config_dword(struct pci_controller *hose, + pci_dev_t dev, + int offset, u32* value) +{ + *value = pciReadConfigReg((PCI_HOST) hose->cfg_addr, offset, PCI_DEV(dev)); + return 0; +} + +static int gt_write_config_dword(struct pci_controller *hose, + pci_dev_t dev, + int offset, u32 value) +{ + pciWriteConfigReg((PCI_HOST)hose->cfg_addr, offset, PCI_DEV(dev), value); + return 0; +} + +/* + * + */ + +static void gt_setup_ide(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ + static const int ide_bar[]={8,4,8,4,0,0}; + u32 bar_response, bar_value; + int bar; + + for (bar=0; bar<6; bar++) + { + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, 0x0); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, &bar_response); + + pciauto_region_allocate(bar_response & PCI_BASE_ADDRESS_SPACE_IO ? + hose->pci_io : hose->pci_mem, ide_bar[bar], &bar_value); + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, bar_value); + } +} + +static void gt_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char pin, irq; + + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + + if(pin == 1) { /* only allow INT A */ + irq = pci_irq_swizzle[(PCI_HOST)hose->cfg_addr][PCI_DEV(dev)]; + if(irq) + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); + } +} + +struct pci_config_table gt_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, + + { } +}; + +struct pci_controller pci0_hose = { + fixup_irq: gt_fixup_irq, + config_table: gt_config_table, +}; + +struct pci_controller pci1_hose = { + fixup_irq: gt_fixup_irq, + config_table: gt_config_table, +}; + +void +pci_init(void) +{ + unsigned int command; + + pci0_hose.first_busno = 0; + pci0_hose.last_busno = 0xff; + + /* PCI memory space */ + pci_set_region(pci0_hose.regions + 0, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_0_MEM_SPACE, + CFG_PCI0_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(pci0_hose.regions + 1, + CFG_PCI0_IO_SPACE_PCI, + CFG_PCI0_IO_SPACE, + CFG_PCI0_IO_SIZE, + PCI_REGION_IO); + + pci_set_ops(&pci0_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + + pci0_hose.region_count = 2; + + pci0_hose.cfg_addr = (unsigned int*) PCI_HOST0; + + pci_register_hose(&pci0_hose); + + pciArbiterEnable(PCI_HOST0); + pciParkingDisable(PCI_HOST0,1,1,1,1,1,1,1); + + command = pciReadConfigReg(PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg(PCI_HOST0, PCI_COMMAND, SELF, command); + + pci0_hose.last_busno = pci_hose_scan(&pci0_hose); + + command = pciReadConfigReg(PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg(PCI_HOST0, PCI_COMMAND, SELF, command); + + pci1_hose.first_busno = pci0_hose.last_busno + 1; + pci1_hose.last_busno = 0xff; + + /* PCI memory space */ + pci_set_region(pci1_hose.regions + 0, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_0_MEM_SPACE, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(pci1_hose.regions + 1, + CFG_PCI1_IO_SPACE_PCI, + CFG_PCI1_IO_SPACE, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + pci_set_ops(&pci1_hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + gt_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + gt_write_config_dword); + + pci1_hose.region_count = 2; + + pci1_hose.cfg_addr = (unsigned int*) PCI_HOST1; + + pci_register_hose(&pci1_hose); + + pciArbiterEnable(PCI_HOST1); + pciParkingDisable(PCI_HOST1,1,1,1,1,1,1,1); + + command = pciReadConfigReg(PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg(PCI_HOST1, PCI_COMMAND, SELF, command); + + pci1_hose.last_busno = pci_hose_scan(&pci1_hose); + + command = pciReadConfigReg(PCI_HOST1, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg(PCI_HOST1, PCI_COMMAND, SELF, command); +} diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c new file mode 100644 index 0000000..ff98e4d --- /dev/null +++ b/board/evb64260/sdram_init.c @@ -0,0 +1,629 @@ +/* + * (C) Copyright 2001 + * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* sdram_init.c - automatic memory sizing */ + +#include <common.h> +#include <74xx_7xx.h> +#include <galileo/memory.h> +#include <galileo/pci.h> +#include <galileo/gt64260R.h> +#include <net.h> + +#include "eth.h" +#include "mpsc.h" +#include "i2c.h" +#include "64260.h" + +/* #define DEBUG */ +#define MAP_PCI + +#ifdef DEBUG +#define DP(x) x +#else +#define DP(x) +#endif + +#define GB (1 << 30) + +/* structure to store the relevant information about an sdram bank */ +typedef struct sdram_info { + uchar drb_size; + uchar registered, ecc; + uchar tpar; + uchar tras_clocks; + uchar burst_len; + uchar banks, slot; + int size; /* detected size, not from I2C but from dram_size() */ +} sdram_info_t; + +#ifdef DEBUG +void dump_dimm_info(struct sdram_info *d) +{ + static const char *ecc_legend[]={""," Parity"," ECC"}; + printf("dimm%s %sDRAM: %dMibytes:\n", + ecc_legend[d->ecc], + d->registered?"R":"", + (d->size>>20)); + printf(" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n", + d->drb_size, d->tpar, d->tras_clocks, d->burst_len, + d->banks, d->slot); +} +#endif + +static int +memory_map_bank(unsigned int bankNo, + unsigned int bankBase, + unsigned int bankLength) +{ +#ifdef DEBUG + if (bankLength > 0) { + printf("mapping bank %d at %08x - %08x\n", + bankNo, bankBase, bankBase + bankLength - 1); + } else { + printf("unmapping bank %d\n", bankNo); + } +#endif + + memoryMapBank(bankNo, bankBase, bankLength); + + return 0; +} + +#ifdef MAP_PCI +static int +memory_map_bank_pci(unsigned int bankNo, + unsigned int bankBase, + unsigned int bankLength) +{ + PCI_HOST host; + for (host=PCI_HOST0;host<=PCI_HOST1;host++) { + const int features= + PREFETCH_ENABLE | + DELAYED_READ_ENABLE | + AGGRESSIVE_PREFETCH | + READ_LINE_AGGRESSIVE_PREFETCH | + READ_MULTI_AGGRESSIVE_PREFETCH | + MAX_BURST_4 | + PCI_NO_SWAP; + + pciMapMemoryBank(host, bankNo, bankBase, bankLength); + + pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase, + bankLength); + + pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength); + } + return 0; +} +#endif + +/* ------------------------------------------------------------------------- */ + +/* much of this code is based on (or is) the code in the pip405 port */ +/* thanks go to the authors of said port - Josh */ + + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short +NS10to10PS(unsigned char spd_byte) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return(ns*100 + ns10*10); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ +static inline unsigned short +NSto10PS(unsigned char spd_byte) +{ + return(spd_byte*100); +} + +#ifdef CONFIG_ZUMA_V2 +static int +check_dimm(uchar slot, sdram_info_t *info) +{ + /* assume 2 dimms, 2 banks each 256M - we dont have an + * dimm i2c so rely on the detection routines later */ + + memset(info, 0, sizeof(*info)); + + info->slot = slot; + info->banks = 2; /* Detect later */ + info->registered = 0; + info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit + but doesn't matter, both do same + thing in setup_sdram() */ + info->tpar = 3; + info->tras_clocks = 5; + info->burst_len = 4; +#ifdef CONFIG_ECC + info->ecc = 0; /* Detect later */ +#endif /* CONFIG_ECC */ + return 0; +} + +#else /* ! CONFIG_ZUMA_V2 */ + +/* This code reads the SPD chip on the sdram and populates + * the array which is passed in with the relevant information */ +static int +check_dimm(uchar slot, sdram_info_t *info) +{ + DECLARE_GLOBAL_DATA_PTR; + uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; + int ret; + uchar rows, cols, sdram_banks, supp_cal, width, cal_val; + ulong tmemclk; + uchar trp_clocks, trcd_clocks; + uchar data[128]; + + get_clocks (); + + tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */ + +#ifdef CONFIG_EVB64260_750CX + if (0 != slot) { + printf("check_dimm: The EVB-64260-750CX only has 1 DIMM,"); + printf(" called with slot=%d insetad!\n", slot); + return 0; + } +#endif + DP(puts("before i2c read\n")); + + ret = i2c_read(addr, 0, 128, data, 0); + + DP(puts("after i2c read\n")); + + /* zero all the values */ + memset(info, 0, sizeof(*info)); + + if (ret) { + DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret)); + return 0; + } + + /* first, do some sanity checks */ + if (data[2] != 0x4) { + printf("Not SDRAM in slot %d\n", slot); + return 0; + } + + /* get various information */ + rows = data[3]; + cols = data[4]; + info->banks = data[5]; + sdram_banks = data[17]; + width = data[13] & 0x7f; + + DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks)); + + /* check if the memory is registered */ + if (data[21] & (BIT1 | BIT4)) + info->registered = 1; + +#ifdef CONFIG_ECC + /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ + info->ecc = (data[11] & 2) >> 1; +#endif + + /* bit 1 is CL2, bit 2 is CL3 */ + supp_cal = (data[18] & 0x6) >> 1; + + /* compute the relevant clock values */ + trp_clocks = (NSto10PS(data[27])+(tmemclk-1)) / tmemclk; + trcd_clocks = (NSto10PS(data[29])+(tmemclk-1)) / tmemclk; + info->tras_clocks = (NSto10PS(data[30])+(tmemclk-1)) / tmemclk; + + DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n", + trp_clocks, trcd_clocks, info->tras_clocks)); + + /* try a CAS latency of 3 first... */ + cal_val = 0; + if (supp_cal & 3) { + if (NS10to10PS(data[9]) <= tmemclk) + cal_val = 3; + } + + /* then 2... */ + if (supp_cal & 2) { + if (NS10to10PS(data[23]) <= tmemclk) + cal_val = 2; + } + + DP(printf("cal_val = %d\n", cal_val)); + + /* bummer, did't work... */ + if (cal_val == 0) { + DP(printf("Couldn't find a good CAS latency\n")); + return 0; + } + + /* get the largest delay -- these values need to all be the same + * see Res#6 */ + info->tpar = cal_val; + if (trp_clocks > info->tpar) + info->tpar = trp_clocks; + if (trcd_clocks > info->tpar) + info->tpar = trcd_clocks; + + DP(printf("tpar set to: %d\n", info->tpar)); + +#ifdef CFG_BROKEN_CL2 + if (info->tpar == 2){ + info->tpar = 3; + DP(printf("tpar fixed-up to: %d\n", info->tpar)); + } +#endif + /* compute the module DRB size */ + info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M; + + DP(printf("drb_size set to: %d\n", info->drb_size)); + + /* find the burst len */ + info->burst_len = data[16] & 0xf; + if ((info->burst_len & 8) == 8) { + info->burst_len = 1; + } else if ((info->burst_len & 4) == 4) { + info->burst_len = 0; + } else { + return 0; + } + + info->slot = slot; + return 0; +} +#endif /* ! CONFIG_ZUMA_V2 */ + +static int +setup_sdram_common(sdram_info_t info[2]) +{ + ulong tmp; + int tpar=2, tras_clocks=5, registered=1, ecc=2; + + if(!info[0].banks && !info[1].banks) return 0; + + if(info[0].banks) { + if(info[0].tpar>tpar) tpar=info[0].tpar; + if(info[0].tras_clocks>tras_clocks) tras_clocks=info[0].tras_clocks; + if(!info[0].registered) registered=0; + if(info[0].ecc!=2) ecc=0; + } + + if(info[1].banks) { + if(info[1].tpar>tpar) tpar=info[1].tpar; + if(info[1].tras_clocks>tras_clocks) tras_clocks=info[1].tras_clocks; + if(!info[1].registered) registered=0; + if(info[1].ecc!=2) ecc=0; + } + + /* SDRAM configuration */ + tmp = GTREGREAD(SDRAM_CONFIGURATION); + + /* Turn on physical interleave if both DIMMs + * have even numbers of banks. */ + if( (info[0].banks == 0 || info[0].banks == 2) && + (info[1].banks == 0 || info[1].banks == 2) ) { + /* physical interleave on */ + tmp &= ~(1 << 15); + } else { + /* physical interleave off */ + tmp |= (1 << 15); + } + + tmp |= (registered << 17); + + /* Use buffer 1 to return read data to the CPU + * See Res #12 */ + tmp |= (1 << 26); + + GT_REG_WRITE(SDRAM_CONFIGURATION, tmp); + DP(printf("SDRAM config: %08x\n", + GTREGREAD(SDRAM_CONFIGURATION))); + + /* SDRAM timing */ + tmp = (((tpar == 3) ? 2 : 1) | + (((tpar == 3) ? 2 : 1) << 2) | + (((tpar == 3) ? 2 : 1) << 4) | + (tras_clocks << 8)); + +#ifdef CONFIG_ECC + /* Setup ECC */ + if (ecc == 2) tmp |= 1<<13; +#endif /* CONFIG_ECC */ + + GT_REG_WRITE(SDRAM_TIMING, tmp); + DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n", + GTREGREAD(SDRAM_TIMING), tpar,tpar,tpar,tras_clocks)); + + /* SDRAM address decode register */ + /* program this with the default value */ + GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2); + DP(printf("SDRAM decode: %08x\n", + GTREGREAD(SDRAM_ADDRESS_DECODE))); + + return 0; +} + +/* sets up the GT properly with information passed in */ +static int +setup_sdram(sdram_info_t *info) +{ + ulong tmp, check; + ulong *addr = 0; + int i; + + /* sanity checking */ + if (! info->banks) return 0; + + /* ---------------------------- */ + /* Program the GT with the discovered data */ + + /* bank parameters */ + tmp = (0xf<<16); /* leave all virt bank pages open */ + + DP(printf("drb_size: %d\n", info->drb_size)); + switch (info->drb_size) { + case 1: + tmp |= (1 << 14); + break; + case 4: + case 8: + tmp |= (2 << 14); + break; + case 16: + case 32: + tmp |= (3 << 14); + break; + default: + printf("Error in dram size calculation\n"); + return 1; + } + + /* SDRAM bank parameters */ + /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ + GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp); + GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp); + DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, info->slot*2, (info->slot*2)+1, tmp)); + + /* set the SDRAM configuration for each bank */ + for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) { + DP(printf("*** Running a MRS cycle for bank %d ***\n", i)); + + /* map the bank */ + memory_map_bank(i, 0, GB/4); + + /* set SDRAM mode */ + GT_REG_WRITE(SDRAM_OPERATION_MODE, 0x3); + check = GTREGREAD(SDRAM_OPERATION_MODE); + + /* dummy write */ + *addr = 0; + + /* wait for the command to complete */ + while ((GTREGREAD(SDRAM_OPERATION_MODE) & (1 << 31)) == 0) + ; + + /* switch back to normal operation mode */ + GT_REG_WRITE(SDRAM_OPERATION_MODE, 0); + check = GTREGREAD(SDRAM_OPERATION_MODE); + + /* unmap the bank */ + memory_map_bank(i, 0, 0); + DP(printf("*** MRS cycle for bank %d done ***\n", i)); + } + + return 0; +} + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +static long int +dram_size(long int *base, long int maxsize) +{ + volatile long int *addr, *b=base; + long int cnt, val, save1, save2; + +#define STARTVAL (1<<20) /* start test at 1M */ + for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + save1=*addr; /* save contents of addr */ + save2=*b; /* save contents of base */ + + *addr=cnt; /* write cnt to addr */ + *b=0; /* put null at base */ + + /* check at base address */ + if ((*b) != 0) { + *addr=save1; /* restore *addr */ + *b=save2; /* restore *b */ + return (0); + } + val = *addr; /* read *addr */ + + *addr=save1; + *b=save2; + + if (val != cnt) { + /* fix boundary condition.. STARTVAL means zero */ + if(cnt==STARTVAL/sizeof(long)) cnt=0; + return (cnt * sizeof(long)); + } + } + return maxsize; +} + +/* ------------------------------------------------------------------------- */ + +/* U-Boot interface function to SDRAM init - this is where all the + * controlling logic happens */ +long int +initdram(int board_type) +{ + ulong checkbank[4] = { [0 ... 3] = 0 }; + int bank_no; + ulong total; + int nhr; + sdram_info_t dimm_info[2]; + + + /* first, use the SPD to get info about the SDRAM */ + + /* check the NHR bit and skip mem init if it's already done */ + nhr = get_hid0() & (1 << 16); + + if (nhr) { + printf("Skipping SDRAM setup due to NHR bit being set\n"); + } else { + /* DIMM0 */ + check_dimm(0, &dimm_info[0]); + + /* DIMM1 */ +#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */ + check_dimm(1, &dimm_info[1]); +#else /* CONFIG_EVB64260_750CX */ + memset(&dimm_info[1], 0, sizeof(sdram_info_t)); +#endif + + /* unmap all banks */ + memory_map_bank(0, 0, 0); + memory_map_bank(1, 0, 0); + memory_map_bank(2, 0, 0); + memory_map_bank(3, 0, 0); + + /* Now, program the GT with the correct values */ + if (setup_sdram_common(dimm_info)) { + printf("Setup common failed.\n"); + } + + if (setup_sdram(&dimm_info[0])) { + printf("Setup for DIMM1 failed.\n"); + } + + if (setup_sdram(&dimm_info[1])) { + printf("Setup for DIMM2 failed.\n"); + } + + /* set the NHR bit */ + set_hid0(get_hid0() | (1 << 16)); + } + /* next, size the SDRAM banks */ + + total = 0; + if (dimm_info[0].banks > 0) checkbank[0] = 1; + if (dimm_info[0].banks > 1) checkbank[1] = 1; + if (dimm_info[0].banks > 2) + printf("Error, SPD claims DIMM1 has >2 banks\n"); + + if (dimm_info[1].banks > 0) checkbank[2] = 1; + if (dimm_info[1].banks > 1) checkbank[3] = 1; + if (dimm_info[1].banks > 2) + printf("Error, SPD claims DIMM2 has >2 banks\n"); + + /* Generic dram sizer: works even if we don't have i2c DIMMs, + * as long as the timing settings are more or less correct */ + + /* + * pass 1: size all the banks, using first bat (0-256M) + * limitation: we only support 256M per bank due to + * us only having 1 BAT for all DRAM + */ + for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + /* skip over banks that are not populated */ + if (! checkbank[bank_no]) + continue; + + DP(printf("checking bank %d\n", bank_no)); + + memory_map_bank(bank_no, 0, GB/4); + checkbank[bank_no] = dram_size(NULL, GB/4); + memory_map_bank(bank_no, 0, 0); + + DP(printf("bank %d %08lx\n", bank_no, checkbank[bank_no])); + } + + /* + * pass 2: contiguously map each bank into physical address + * space. + */ + dimm_info[0].banks=dimm_info[1].banks=0; + for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + if(!checkbank[bank_no]) continue; + + dimm_info[bank_no/2].banks++; + dimm_info[bank_no/2].size+=checkbank[bank_no]; + + memory_map_bank(bank_no, total, checkbank[bank_no]); +#ifdef MAP_PCI + memory_map_bank_pci(bank_no, total, checkbank[bank_no]); +#endif + total += checkbank[bank_no]; + } + +#ifdef CONFIG_ECC +#ifdef CONFIG_ZUMA_V2 + /* + * We always enable ECC when bank 2 and 3 are unpopulated + * If we 2 or 3 are populated, we CAN'T support ECC. + * (Zuma boards only support ECC in banks 0 and 1; assume that + * in that configuration, ECC chips are mounted, even for stacked + * chips) + */ + if (checkbank[2]==0 && checkbank[3]==0) { + dimm_info[0].ecc=2; + GT_REG_WRITE(SDRAM_TIMING, GTREGREAD(SDRAM_TIMING) | (1 << 13)); + /* TODO: do we have to run MRS cycles again? */ + } +#endif /* CONFIG_ZUMA_V2 */ + + if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) { + puts("[ECC] "); + } +#endif /* CONFIG_ECC */ + +#ifdef DEBUG + dump_dimm_info(&dimm_info[0]); + dump_dimm_info(&dimm_info[1]); +#endif + /* TODO: return at MOST 256M? */ + /* return total > GB/4 ? GB/4 : total; */ + return total; +} diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c new file mode 100644 index 0000000..d9c7a15 --- /dev/null +++ b/board/evb64260/serial.c @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2001 + * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * serial.c - serial support for the gal ev board + */ + +/* supports both the 16650 duart and the MPSC */ + +#include <common.h> +#include <command.h> +#include <galileo/memory.h> + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +#include <ns16550.h> +#endif + +#include "serial.h" + +#include "mpsc.h" + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, + (NS16550_t) CFG_NS16550_COM2 }; +#endif + +#ifdef CONFIG_MPSC + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; +#endif + + mpsc_init(gd->baudrate); + + /* init the DUART chans so that KGDB in the kernel can use them */ +#ifdef CFG_INIT_CHAN1 + NS16550_reinit(COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit(COM_PORTS[1], clock_divisor); +#endif + return (0); +} + +void +serial_putc(const char c) +{ + if (c == '\n') + mpsc_putchar('\r'); + + mpsc_putchar(c); +} + +int +serial_getc(void) +{ + return mpsc_getchar(); +} + +int +serial_tstc(void) +{ + return mpsc_test_char(); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate); +} + +#else /* ! CONFIG_MPSC */ + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + (void)NS16550_init(COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + (void)NS16550_init(COM_PORTS[1], clock_divisor); +#endif + + return (0); +} + +void +serial_putc(const char c) +{ + if (c == '\n') + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); + + NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); +} + +int +serial_getc(void) +{ + return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); +} + +int +serial_tstc(void) +{ + return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); +} + +void +serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + +#ifdef CFG_INIT_CHAN1 + NS16550_reinit(COM_PORTS[0], clock_divisor); +#endif +#ifdef CFG_INIT_CHAN2 + NS16550_reinit(COM_PORTS[1], clock_divisor); +#endif +} + +#endif /* CONFIG_MPSC */ + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +void +kgdb_serial_init(void) +{ +} + +void +putDebugChar (int c) +{ + serial_putc (c); +} + +void +putDebugStr (const char *str) +{ + serial_puts (str); +} + +int +getDebugChar (void) +{ + return serial_getc(); +} + +void +kgdb_interruptible (int yes) +{ + return; +} +#endif /* CFG_CMD_KGDB */ |