Merge git://git.denx.de/u-boot-fsl-qoriq

8 files changed, 195 insertions, 17 deletions

diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile
index 2a4452e..930c690 100644
--- a/board/freescale/ls1043ardb/Makefile
+++ b/board/freescale/ls1043ardb/Makefile
@@ -7,6 +7,6 @@
 obj-y += ddr.o
 obj-y += ls1043ardb.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-$(CONFIG_NET) += eth.o
 obj-y += cpld.o
 endif
diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile
index b92ed0b..4076558 100644
--- a/board/freescale/ls1046ardb/Makefile
+++ b/board/freescale/ls1046ardb/Makefile
@@ -7,6 +7,6 @@
 obj-y += ddr.o
 obj-y += ls1046ardb.o
 ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+obj-$(CONFIG_NET) += eth.o
 obj-y += cpld.o
 endif
diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
index 1ef7d47..a38c9d4 100644
--- a/board/freescale/ls1046ardb/README
+++ b/board/freescale/ls1046ardb/README
@@ -59,14 +59,14 @@ Start Address	 End Address	 Description		Size
 QSPI flash map:
 Start Address    End Address     Description		Size
 0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI		1MB
-0x00_4010_0000 - 0x00_401F_FFFF  U-Boot 		1MB
-0x00_4020_0000 - 0x00_402F_FFFF  U-Boot Env		1MB
-0x00_4030_0000 - 0x00_403F_FFFF  FMan ucode		1MB
-0x00_4040_0000 - 0x00_404F_FFFF  UEFI			1MB
-0x00_4050_0000 - 0x00_406F_FFFF  PPA			2MB
-0x00_4070_0000 - 0x00_408F_FFFF  Secure boot header
-			         + bootscript		2MB
-0x00_4090_0000 - 0x00_40FF_FFFF  Reserved		7MB
+0x00_4010_0000 - 0x00_402F_FFFF  U-Boot 		2MB
+0x00_4030_0000 - 0x00_403F_FFFF  U-Boot Env		1MB
+0x00_4040_0000 - 0x00_405F_FFFF  PPA			2MB
+0x00_4060_0000 - 0x00_408F_FFFF  Secure boot header
+				 + bootscript		3MB
+0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
+0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
+0x00_4098_0000 - 0x00_40FF_FFFF  Reserved		6MB
 0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
 
 Booting Options
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 2808bd5..cad860e 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -89,6 +89,19 @@ c) NAND boot
 d) SD boot
 e) QSPI boot
 
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Secure Headers			0x00600000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
 Environment Variables
 ---------------------
 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index 2f0465f..8f64642 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -16,3 +16,21 @@ config SYS_CONFIG_NAME
 source "board/freescale/common/Kconfig"
 
 endif
+
+if TARGET_LS2081ARDB
+
+config SYS_BOARD
+	default "ls2080ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls2080ardb"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 759a146..91f13ea 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -7,6 +7,16 @@ F:	include/configs/ls2080ardb.h
 F:	configs/ls2080ardb_defconfig
 F:	configs/ls2080ardb_nand_defconfig
 
+LS2088A_QSPI-boot BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2088ardb_qspi_defconfig
+
+LS2081ARDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2081ardb_defconfig
+
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
 S:	Maintained
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 0c9c574..205c45c 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -4,10 +4,14 @@ The LS2080A Reference Design (RDB) is a high-performance computing,
 evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
 Layerscape Architecture processor.
 
-LS2080A, LS2088A SoC Overview
---------------------
+The LS2081A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2081A
+Layerscape Architecture processor.More details in below sections
+
+LS2080A, LS2088A, LS2081A SoC Overview
+--------------------------------------
 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
-LS2088A SoC overview.
+LS2081A, LS2088A SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
@@ -38,11 +42,22 @@ LS2088A SoC overview.
  - UART
  - ARM JTAG support
 
+ LS2081ARDB board Overview
+ -------------------------
+ LS2081ARDB board is similar to LS2080ARDB board
+ with few differences like
+  - Hosts LS2081A SoC
+  - Default boot source is QSPI-boot
+  - Does not have IFC interface
+  - RTC and QSPI flash devices are different
+  - Provides QIXIS access via I2C
+
 Memory map from core's view
 ----------------------------
 0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
 0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
 0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_2000_0000 .. 0x00_2FFF_FFFF	QSPI region #1
 0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
 0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
 0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
@@ -68,6 +83,45 @@ Booting Options
 ---------------
 a) NOR boot
 b) NAND boot
+c) QSPI boot
+
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Secure Headers			0x00600000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
+cfg_rcw_src switches needs to be changed for booting from different option.
+Refer to board documentation for correct switch setting.
+
+QSPI boot details
+===================
+Supported only for
+ LS2088ARDB RevF board with LS2088A SoC.
+
+Images needs to be copied to QSPI flash
+as per memory map given below.
+
+Memory map for QSPI flash
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
 
 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
 -------------------------------------------------------------------
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index ea05ec6..df2d768 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2017 NXP Semiconductors
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -22,8 +23,10 @@
 #include <asm/arch/ppa.h>
 #include <fsl_sec.h>
 
+#ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
 #include "ls2080ardb_qixis.h"
+#endif
 #include "../common/vid.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
@@ -57,12 +60,53 @@ unsigned long long get_qixis_addr(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
+#endif
 	char buf[15];
 
 	cpu_name(buf);
 	printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, ", (sw & 0xf) + 'A');
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+	switch (sw) {
+	case 0:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 1:
+		puts("boot from QSPI DEV#1\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 2:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 3:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 4:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
+		break;
+	default:
+		printf("invalid setting of SW%u\n", sw);
+		break;
+	}
+#endif
+	puts("SERDES1 Reference : ");
+	printf("Clock1 = 100MHz ");
+	printf("Clock2 = 161.13MHz");
+#else
+#ifdef CONFIG_FSL_QIXIS
 	sw = QIXIS_READ(arch);
 	printf("Board Arch: V%d, ", sw >> 4);
 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
@@ -78,10 +122,11 @@ int checkboard(void)
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 
 	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
+#endif
 	puts("SERDES1 Reference : ");
 	printf("Clock1 = 156.25MHz ");
 	printf("Clock2 = 156.25MHz");
+#endif
 
 	puts("\nSERDES2 Reference : ");
 	printf("Clock1 = 100MHz ");
@@ -92,6 +137,7 @@ int checkboard(void)
 
 unsigned long get_board_sys_clk(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 
 	switch (sysclk_conf & 0x0F) {
@@ -110,7 +156,8 @@ unsigned long get_board_sys_clk(void)
 	case QIXIS_SYSCLK_166:
 		return 166666666;
 	}
-	return 66666666;
+#endif
+	return 100000000;
 }
 
 int select_i2c_ch_pca9547(u8 ch)
@@ -133,6 +180,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
 
 int config_board_mux(int ctrl_type)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 reg5;
 
 	reg5 = QIXIS_READ(brdcfg[5]);
@@ -150,7 +198,7 @@ int config_board_mux(int ctrl_type)
 	}
 
 	QIXIS_WRITE(brdcfg[5], reg5);
-
+#endif
 	return 0;
 }
 
@@ -180,8 +228,9 @@ int board_init(void)
 #endif
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
+#ifdef CONFIG_FSL_QIXIS
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
-
+#endif
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
@@ -199,12 +248,40 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
 	fsl_lsch3_early_init_f();
 	return 0;
 }
 
 int misc_init_r(void)
 {
+#ifdef CONFIG_FSL_QIXIS
+	/*
+	 * LS2081ARDB has smart voltage translator which needs
+	 * to be programmed as below
+	 */
+#ifndef CONFIG_TARGET_LS2081ARDB
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	/*
+	 * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
+	 * which needs to be programmed to enable high speed SD interface
+	 * by setting GPIO4_10 output to zero
+	 */
+	if ((sw & 0xf) == 0x5) {
+#endif
+		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
+					    in_le32(GPIO4_GPDIR_ADDR)));
+		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
+					    in_le32(GPIO4_GPDAT_ADDR)));
+#ifndef CONFIG_TARGET_LS2081ARDB
+	}
+#endif
+#endif
+
 	if (hwconfig("sdhc"))
 		config_board_mux(MUX_TYPE_SDHC);
 
@@ -301,6 +378,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 void qixis_dump_switch(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	int i, nr_of_cfgsw;
 
 	QIXIS_WRITE(cms[0], 0x00);
@@ -311,6 +389,7 @@ void qixis_dump_switch(void)
 		QIXIS_WRITE(cms[0], i);
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
+#endif
 }
 
 /*
@@ -321,6 +400,8 @@ void update_spd_address(unsigned int ctrl_num,
 			unsigned int slot,
 			unsigned int *addr)
 {
+#ifndef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
 
 	sw = QIXIS_READ(arch);
@@ -330,4 +411,6 @@ void update_spd_address(unsigned int ctrl_num,
 		else if (ctrl_num == 1 && slot == 1)
 			*addr = SPD_EEPROM_ADDRESS3;
 	}
+#endif
+#endif
 }