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| author | Alexander Stein <alexanders83@web.de> | 2015-07-24 07:22:11 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-13 00:47:41 (GMT) |
| commit | 060f9bf57b1dc1f9260bc1b999d054141b87d7d2 (patch) | |
| tree | ac71ebcf77ce3b3c9e163542dc06d16e28fa6a64 /board/lwmon5/MAINTAINERS | |
| parent | 2085ae74dee47ed3da63416aac0305936b43eeea (diff) | |
| download | u-boot-fsl-qoriq-060f9bf57b1dc1f9260bc1b999d054141b87d7d2.tar.xz | |
ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Diffstat (limited to 'board/lwmon5/MAINTAINERS')
0 files changed, 0 insertions, 0 deletions