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| author | Stefan Roese <sr@denx.de> | 2010-09-11 07:31:43 (GMT) |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-09-23 07:02:05 (GMT) |
| commit | 5e7abce99163a00b8d267cc8045f06b498728288 (patch) | |
| tree | 33da20a6f8524f7a8929cc4f8c003708a5f0a6e8 /board/netstal | |
| parent | 098877628888f28f321b8a61a9b0b982a969e415 (diff) | |
| download | u-boot-fsl-qoriq-5e7abce99163a00b8d267cc8045f06b498728288.tar.xz | |
ppc4xx: Big header cleanup, mostly PPC440 related
This patch starts a bit PPC4xx header cleanup. First patch mostly
touches PPC440 files. A later patch will touch the PPC405 files as well.
This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/netstal')
| -rw-r--r-- | board/netstal/hcu5/hcu5.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index b15f99e..f94d05b 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -327,7 +327,7 @@ int board_with_pci(void) u32 reg; mfsdr(SDR0_PCI0, reg); - return (reg & SDR0_XCR_PAE_MASK); + return (reg & SDR0_PCI0_PAE_MASK); } /* @@ -352,28 +352,28 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ + mfsdr(SDR0_AMP1, addr); + mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3A0_ACR); + mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */ /* * Set priority for all PLB4 devices to 0. */ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); /* Sequoia */ + mfsdr(SDR0_AMP0, addr); + mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4A0_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4A0_ACR, addr); /* Sequoia */ /* * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. * Workaround: Disable write pipelining to DDR SDRAM by setting - * PLB0_ACR[WRP] = 0. + * PLB4A0_ACR[WRP] = 0. */ - mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB4A0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ - mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB4A1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return board_with_pci(); } |